Datasheet AD4001, AD4005 (Analog Devices) - 34

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AD4001/AD4005 Data Sheet CS MODE, 4-WIRE WITH BUSY INDICATOR
SDI must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion This mode is typically used when a AD4001/AD4005 device is time to guarantee the generation of the busy signal indicator. connected to an SPI-compatible digital host with an interrupt input (IRQ), and when it is desired to keep CNV, which samples When the conversion is complete, SDO goes from high the analog input, independent of the signal used to select the impedance to low impedance. With a pull-up resistor of 1 kΩ data reading. This independence is particularly important in on the SDO line, this transition can be used as an interrupt signal applications where low jitter on CNV is desired. to initiate the data readback controlled by the digital host. The AD4001/AD4005 then enter the acquisition phase and power The connection diagram is shown in Figure 62, and the down. The data bits are then clocked out, MSB first, by subsequent corresponding timing diagram is shown in Figure 63. SCK falling edges. The data is valid on both SCK edges. Although With SDI high, a rising edge on CNV initiates a conversion, the rising edge can capture the data, a digital host using the SCK selects the CS mode, and forces SDO to high impedance. In this falling edge allows a faster reading rate, provided it has an mode, CNV must be held high during the conversion phase and acceptable hold time. After the optional 17th SCK falling edge or the subsequent data readback. If SDI and CNV are low, SDO is when SDI goes high (whichever occurs first), SDO returns to driven low. Prior to the minimum conversion time, SDI can high impedance. select other SPI devices, such as analog multiplexers; however,
CS1 CONVERT VIO CNV DIGITAL HOST 1kΩ AD4001/ SDI SDO DATA IN AD4005 SCK IRQ CLK
-132 15368 Figure 62. CS Mode, 4-Wire with Busy Indicator Connection Diagram
tCYC CNV tACQ ACQUISITION CONVERSION ACQUISITION tCONV t t SSDICNV QUIET2 SDI tSCK tHSDICNV tSCKL SCK 1 2 3 15 16 17 t t SCKH HSDO tDSDO tDIS tEN SDO D15 D14 D1 D0
033 15368- Figure 63. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing Diagram Rev. B | Page 34 of 37 Document Outline Features Applications General Description Functional Block Diagram Table of Contents Revision History Specifications Timing Specifications Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configurations and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Circuit Information Converter Operation Transfer Functions Applications Information Typical Application Diagrams Analog Inputs Input Overvoltage Clamp Circuit Differential Input Considerations Switched Capacitor Input RC Filter Values Driver Amplifier Choice Single to Differential Driver High Frequency Input Signals Multiplexed Applications Ease of Drive Features Input Span Compression High-Z Mode Long Acquisition Phase Voltage Reference Input Power Supply Digital Interface Register Read/Write Functionality Status Word /CS Mode, 3-Wire Turbo Mode /CS Mode, 3-Wire Without Busy Indicator /CS Mode, 3-Wire with Busy Indicator /CS Mode, 4-Wire Turbo Mode /CS Mode, 4-Wire Without Busy Indicator /CS Mode, 4-Wire with Busy Indicator Daisy-Chain Mode Layout Guidelines Evaluating the AD4001/AD4005 Performance Outline Dimensions Ordering Guide