Datasheet AD9695 (Analog Devices) - 132

link to page 41 link to page 42 link to page 38 link to page 38 link to page 41 link to page 42 link to page 38 link to page 38 link to page 29 link to page 34
Data Sheet AD9695 Address Name Bits Bit Name Settings Description Reset Access
0x0E00 to Programmable [7:0] Programmable Filter X Refer to the I coefficient table (Table 14) 0x0 R/W 0x0E7F Filter X Coefficient 0 to and the Q coefficient table (Table 15) in Coefficient x Programmable Filter X the Programmable Finite Impulse Coefficient 127 Response (FIR) Filters section for details. Coefficients are only applied after the chip transfer bit (Register 0x000F, Bit 0) is set. 0x0F00 to Programmable [7:0] Programmable Filter Y Refer to the I coefficient table (Table 14) 0x0 R/W 0x0F7F Filter Y Coefficient 0 to and the Q coefficient table (Table 15) in Coefficient x Programmable Filter Y the Programmable Finite Impulse Coefficient 127 Response (FIR) Filters section for details. Coefficients are only applied after the chip transfer bit (Register 0x000F, Bit 0) is set. VREF/Analog Input Control Registers 0x0701 DC Offset [7] DC Offset Calibration 0 Disabled (must set to 0 when 0x0 R/W Calibration Enable 1 Register 0x073B, Bit 7 = 1). Control 1 (local) 1 Enabled (must set to 1 when Register 0x073B, Bit 7 = 0). [6:0] Reserved 110 Reserved. 0x6 R 0x073B DC Offset [7] DC Offset Calibration 0 Enabled (must set to 0 when 0x1 R/W Calibration Enable 2 Register 0x0701, Bit 7 = 1). Control 2 (local) 1 Disabled (must set to 1 when Register 0x0701, Bit 7 = 0). [6:0] Reserved 111111 Reserved. 0x3F R 0x18A6 VREF control [7:1] Reserved Reserved. 0x0 R 0 VREF control 0 Internal reference. 0x0 R/W 1 External reference. 0x18E3 External VCM 7 Reserved Reserved. 0x0 R buffer control 6 External VCM buffer 0 Disable. 0x0 R/W 1 Enable. [5:0] External VCM buffer See the Input Common Mode section. 0x0 R/W [5:0] 0x18E6 Temperature [7:0] Temperature diode See the Temperature Diode section. 0x0 R/W diode export location select 0x00 Central diode. VREF pin = high-Z. 0x01 Central diode. VREF pin = 1× diode voltage output. 0x02 Central diode. VREF pin = 20× diode voltage output. 0x03 Central diode. VREF pin = GND. 0x40 Channel A diode. VREF pin = high-Z. 0x41 Channel A diode. VREF pin = 1× diode voltage output. 0x42 Channel A diode. VREF pin = 20× diode voltage output. 0x43 Channel A diode. VREF pin = GND. 0x50 Channel B diode. VREF pin = high-Z. 0x51 Channel B diode. VREF pin = 1× diode voltage output. 0x52 Channel B diode. VREF pin = 20× diode voltage output. 0x53 Channel B diode. VREF pin = GND. 0x1908 Analog input [7:3] Reserved Reserved. 0x0 R control (local) 2 Enable dc coupling 0 Analog input optimized for ac coupling. 0x0 R/W 1 Analog input optimized for dc coupling. [1:0] Reserved Reserved. 0x0 R Rev. 0 | Page 131 of 135 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION PRODUCT HIGHLIGHTS SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS—1300 MSPS AC SPECIFICATIONS—625 MSPS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 1300 MSPS 625 MSPS EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Absolute Maximum Input Swing Dither VOLTAGE REFERENCE DC OFFSET CALIBRATION CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay and Superfine Delay Adjust Clock Coupling Considerations Clock Jitter Considerations POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) ADC APPLICATION MODES AND JESD204B Tx CONVERTER MAPPING PROGRAMMABLE FINITE IMPULSE RESPONSE (FIR) FILTERS SUPPORTED MODES PROGRAMMING INSTRUCTIONS DIGITAL DOWNCONVERTER (DDC) DDC I/Q INPUT SELECTION DDC I/Q OUTPUT SELECTION DDC GENERAL DESCRIPTION DDC FREQUENCY TRANSLATION DDC Frequency Translation General Description Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO Description DDC NCO Programmable Modulus Mode DDC NCO Coherent Mode NCO FTW/POW/MAW/MAB Description NCO FTW/POW/MAW/MAB Programmable Modulus Mode NCO FTW/POW/MAW/MAB Coherent Mode NCO Channel Selection GPIO Level Control Mode GPIO Edge Control Mode Register Map Mode Setting Up the Multichannel NCO Feature NCO Synchronization NCO Multichip Synchronization NCO Multichip Synchronization at Startup NCO Multichip Synchronization During Normal Operation DDC Mixer Description DDC NCO + Mixer Loss and SFDR DDC DECIMATION FILTERS HB4 Filter Description HB3 Filter Description HB2 Filter Description HB1 Filter Description TB2 Filter Description TB1 Filter Description FB2 Filter Description DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DDC MIXED DECIMATION SETTINGS DDC EXAMPLE CONFIGURATIONS SIGNAL MONITOR SPORT OVER JESD204B DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls Deemphasis Phase-Locked Loop (PLL) SETTING UP THEAD9695 DIGITAL INTERFACE Example Setup 1—Full Bandwidth Mode Example Setup 2—ADC with DDC Option (Two ADCs Plus Two DDCs) DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency registers MULTICHIP SYNCHRONIZATION NORMAL MODE TIMESTAMP MODE SYSREF± INPUT SYREF± Control Features SYSREF± SETUP/HOLD WINDOW MONITOR LATENCY END TO END TOTAL LATENCY EXAMPLE LATENCY CALCULATIONS LMFC REFERENCED LATENCY TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE (SPI) CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel Specific Registers SPI Soft Reset MEMORY MAP REGISTERS APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS LAYOUT GUIDELINES AVDD1_SR (PIN 57) AND AGND_SR (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE