Datasheet LTC3833 (Analog Devices) - 8

LTC3833
PIN FUNCTIONS (FE/UDC) PGOOD (Pin 1/Pin 17):
Power Good Indicator Output.
ITH (Pin 8/Pin 4):
Current Control Voltage and Switch- This open-drain logic output is pulled to ground when ing Regulator Compensation Point. The current sense the output voltage is outside of a ±7.5% window around threshold increases with this control voltage which ranges the regulation point. from 0V to 2.4V.
SENSE+ (Pin 2/Pin 18):
Differential Current Sensing (+)
VRNG (Pin 9/Pin 5):
Current Sense Voltage Range Input. Input. For RSENSE current sensing, Kelvin (4-wire) connect The maximum allowed sense voltage between SENSE+ and SENSE+ and SENSE– pins across the sense resistor. For SENSE– is equal to 0.05 • VRNG. If VRNG is tied to SGND, DCR sensing, Kelvin connect SENSE+ and SENSE– pins the device operates with a maximum sense voltage of across the sense filter capacitor. 30mV. If VRNG is tied to INTVCC, the device operates with
SENSE– (Pin 3/Pin 19):
Differential Current Sensing (–) a maximum sense voltage of 50mV. Input. For RSENSE current sensing, Kelvin (4-wire) connect
RT (Pin 10/Pin 6):
Switching Frequency Programming Pin. SENSE+ and SENSE– pins across the sense resistor. For Connect an external resistor from RT to signal ground to DCR sensing, Kelvin connect SENSE+ and SENSE– pins program the switching frequency between 200kHz and across the sense filter capacitor. 2MHz. An external clock applied to MODE/PLLIN must
V
be within ±30% of this free-running frequency to ensure
OUT (Pin 4/Pin 20):
Output voltage sense for adjusting the TG on-time for constant frequency operation. Tying frequency lock. this pin to the local output (instead of remote output)
RUN (Pin 11/Pin 7):
Digital Run Control Input. RUN self is recommended for most applications. This pin can be biases high with an internal 1.3µA pull-up. Forcing RUN programmed as needed for achieving the steady-state below 1.2V turns off TG and BG. Taking RUN below 0.75V on-time required for constant frequency operation. shuts down all bias and places the LTC3833 into micropower
V –
shutdown mode of approximately 15μA.
OSNS (Pin 5/Pin 1):
Differential Output Sensing (–) Input. Connect this pin to the negative terminal of the
EXTVCC (Pin 12/Pin 8):
External VCC Input. When EXT- output capacitor. There is a bias current of 35µA (typical) VCC exceeds 4.6V, an internal switch connects this pin to flowing out of this pin. INTVCC and shuts down the internal regulator so that the
V +
controller and gate drive power is drawn from EXTVCC.
OSNS (Pin 6/Pin 2):
Differential Output Sensing (+) Input. Connect this pin to the feedback resistor divider between EXTVCC should not exceed VIN. the positive and negative output capacitor terminals. In
MODE/PLLIN (Pin 13/Pin 9):
External Clock Synchroniza- nominal operation the LTC3833 will regulate the differen- tion Input and/or Forced Continuous Mode Input. When an tial output voltage which is divided down to 0.6V by the external clock is applied to this pin, the rising TG signal will feedback resistor divider. be synchronized with the rising edge of the external clock.
TRACK/SS (Pin 7/Pin 3):
External Tracking and Soft-Start Additionally, this pin determines operation under light load Input. The LTC3833 regulates the differential feedback volt- conditions. When either a clock input is detected or MODE/ age (V + – PLLIN is tied to INTVCC, forced continuous mode operation OSNS − VOSNS ) to the smaller of 0.6V or the voltage on the TRACK/SS pin. An internal 1.0μA pull-up current is selected. Tying this pin to SGND allows discontinuous source is connected to this pin. A capacitor to ground at pulse-skipping mode operation at light loads. this pin sets the ramp time to the final regulated output voltage. Alternatively, another voltage supply connected through a resistor divider to this pin allows the output to track the other supply during start-up. 3833f 8