Datasheet LTC3709 (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | Fast 2-Phase, No RSENSE , Synchronous DC/DC Controller with Tracking/Sequencing |
| 页数 / 页 | 24 / 8 — PI FU CTIO S (QFN/SSOP). NC (Pin 12/Pins 1, 17, 18, 19, 20):. TG1, TG2 … |
| 文件格式/大小 | PDF / 329 Kb |
| 文件语言 | 英语 |
PI FU CTIO S (QFN/SSOP). NC (Pin 12/Pins 1, 17, 18, 19, 20):. TG1, TG2 (Pins 27, 14/Pins 35, 22):. VCC (Pin 17/Pin 25):
该数据表的模型线
文件文字版本
LTC3709
U U U PI FU CTIO S (QFN/SSOP) NC (Pin 12/Pins 1, 17, 18, 19, 20):
No Connect.
TG1, TG2 (Pins 27, 14/Pins 35, 22):
Top Gate Drive. Drives the top N-channel MOSFET with a voltage swing
VCC (Pin 17/Pin 25):
Main Input Supply. Decouple this pin equal to DRV to SGND with an RC filter (1Ω, 0.1µF). CC superimposed on the switch node voltage SW.
DRVCC (Pin 21/Pin 29):
Driver Supply. Provides supply to
BOOST1, BOOST2 (Pins 28, 13/Pins 36, 21):
Boosted the driver for the bottom gate. Also used for charging the Floating Driver Supply. The (+) terminal of the bootstrap bootstrap capacitor. capacitor CB connects here. This pin swings from a diode
BG1, BG2 (Pins 22, 20/Pins 30, 28):
Bottom Gate Drive. voltage drop below DRVCC up to VIN + DRVCC. Drives the gate of the bottom N-channel MOSFET between
PGOOD (Pin 29/Pin 2):
Power Good Output. Open-drain ground and DRVCC. logic output that is pulled to ground when output voltage
PGND1, PGND2 (Pins 23, 19/Pins 31, 27):
Power Ground. is not within ±10% of the regulation point. The output Connect this pin closely to the source of the bottom N- voltage must be out of regulation for at least 100µs before channel MOSFET, the (–) terminal of CDRVCC and the (–) ter- the power good output is pulled to ground. minal of CIN.
ION (Pin 30/Pin 3):
On-Time Current Input. Tie a resistor
SENSE1–, SENSE2– (Pins 24, 18/Pins 32, 26):
Current from VIN to this pin to set the one-shot timer current and Sense Comparator Input. The (–) input to the current thereby set the switching frequency. comparator is used to accurately Kelvin sense the bottom
FCB (Pin 31/Pin 4):
Forced Continuous and External Clock side of the sense resistor or MOSFET. Input. Tie this pin to ground to force continuous synchro-
SENSE1+, SENSE2+ (Pins 25, 16/Pins 33, 24):
Current nous operation or to VCC to enable discontinuous mode Sense Comparator Input. The (+) input to the current operation at light load. Feeding an external clock signal comparator is normally connected to the SW node unless into this pin will synchronize the LTC3709 to the external using a sense resistor (see Applications Information). clock and enable forced continuous mode.
SW1, SW2 (Pins 26, 15/Pins 34, 23):
Switch Node. The
VRNG (Pin 32/Pin 5):
Sense Voltage Range Input. The volt- (–) terminal of the bootstrap capacitor CB connects here. age at this pin is ten times the nominal sense voltage at maxi- This pin swings from a Schottky diode voltage drop below mum output current and can be programmed from 0.5V to ground up to VIN. 2V. The sense voltage defaults to 70mV when this pin is tied to ground, 140mV when tied to VCC. 3709fb 8
U U U PI FU CTIO S (QFN/SSOP) NC (Pin 12/Pins 1, 17, 18, 19, 20):
No Connect.
TG1, TG2 (Pins 27, 14/Pins 35, 22):
Top Gate Drive. Drives the top N-channel MOSFET with a voltage swing
VCC (Pin 17/Pin 25):
Main Input Supply. Decouple this pin equal to DRV to SGND with an RC filter (1Ω, 0.1µF). CC superimposed on the switch node voltage SW.
DRVCC (Pin 21/Pin 29):
Driver Supply. Provides supply to
BOOST1, BOOST2 (Pins 28, 13/Pins 36, 21):
Boosted the driver for the bottom gate. Also used for charging the Floating Driver Supply. The (+) terminal of the bootstrap bootstrap capacitor. capacitor CB connects here. This pin swings from a diode
BG1, BG2 (Pins 22, 20/Pins 30, 28):
Bottom Gate Drive. voltage drop below DRVCC up to VIN + DRVCC. Drives the gate of the bottom N-channel MOSFET between
PGOOD (Pin 29/Pin 2):
Power Good Output. Open-drain ground and DRVCC. logic output that is pulled to ground when output voltage
PGND1, PGND2 (Pins 23, 19/Pins 31, 27):
Power Ground. is not within ±10% of the regulation point. The output Connect this pin closely to the source of the bottom N- voltage must be out of regulation for at least 100µs before channel MOSFET, the (–) terminal of CDRVCC and the (–) ter- the power good output is pulled to ground. minal of CIN.
ION (Pin 30/Pin 3):
On-Time Current Input. Tie a resistor
SENSE1–, SENSE2– (Pins 24, 18/Pins 32, 26):
Current from VIN to this pin to set the one-shot timer current and Sense Comparator Input. The (–) input to the current thereby set the switching frequency. comparator is used to accurately Kelvin sense the bottom
FCB (Pin 31/Pin 4):
Forced Continuous and External Clock side of the sense resistor or MOSFET. Input. Tie this pin to ground to force continuous synchro-
SENSE1+, SENSE2+ (Pins 25, 16/Pins 33, 24):
Current nous operation or to VCC to enable discontinuous mode Sense Comparator Input. The (+) input to the current operation at light load. Feeding an external clock signal comparator is normally connected to the SW node unless into this pin will synchronize the LTC3709 to the external using a sense resistor (see Applications Information). clock and enable forced continuous mode.
SW1, SW2 (Pins 26, 15/Pins 34, 23):
Switch Node. The
VRNG (Pin 32/Pin 5):
Sense Voltage Range Input. The volt- (–) terminal of the bootstrap capacitor CB connects here. age at this pin is ten times the nominal sense voltage at maxi- This pin swings from a Schottky diode voltage drop below mum output current and can be programmed from 0.5V to ground up to VIN. 2V. The sense voltage defaults to 70mV when this pin is tied to ground, 140mV when tied to VCC. 3709fb 8