Datasheet LTC2217 (Analog Devices) - 14
| 制造商 | Analog Devices |
| 描述 | 16-Bit, 105Msps Low Noise ADC |
| 页数 / 页 | 32 / 14 — PIN FUNCTIONS. For CMOS Mode. Full Rate or Demultiplexed. CLKOUTB (Pin … |
| 文件格式/大小 | PDF / 1.3 Mb |
| 文件语言 | 英语 |
PIN FUNCTIONS. For CMOS Mode. Full Rate or Demultiplexed. CLKOUTB (Pin 40):. SENSE (Pin 1):. CLKOUTA (Pin 41):
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LTC2217
PIN FUNCTIONS For CMOS Mode. Full Rate or Demultiplexed CLKOUTB (Pin 40):
Data Valid Output. CLKOUTB will toggle
SENSE (Pin 1):
Reference Mode Select and External at the sample rate in full rate CMOS mode or at 1/2 the Reference Input. Tie SENSE to V sample rate in demultiplexed mode. Latch the data on the DD to select the internal 2.5V bandgap reference. An external reference of 2.5V or falling edge of CLKOUTB. 1.25V may be used; both reference values will set a full
CLKOUTA (Pin 41):
Inverted Data Valid Output. CLKOUTA scale ADC range of 2.75V. will toggle at the sample rate in full rate CMOS mode or
GND (Pins 2, 4, 7, 10, 11, 14, 18):
ADC Power Ground. at 1/2 the sample rate in demultiplexed mode. Latch the data on the rising edge of CLKOUTA.
VCM (Pin 3):
1.575V Output. Optimum voltage for input com- mon mode. Must be bypassed to ground with a minimum
DA0-DA15 (Pins 42-48 and 51-59):
Digital Outputs, A Bus. of 2.2μF. Ceramic chip capacitors are recommended. DA15 is the MSB. Output bus for full rate CMOS mode and demultiplexed mode.
VDD (Pins 5, 6, 15, 16, 17):
3.3V Analog Supply Pin. Bypass to GND with 1μF ceramic chip capacitors.
OFA (Pin 60):
Over/Under Flow Digital Output for the A Bus. OFA is high when an over or under fl ow has occurred
A + IN (Pin 8):
Positive Differential Analog Input. on the A bus.
A – IN (Pin 9):
Negative Differential Analog Input.
LVDS (Pin 61):
Data Output Mode Select Pin. Connecting
ENC+ (Pin 12):
Positive Differential Encode Input. The LVDS to 0V selects full rate CMOS mode. Connecting LVDS sampled analog input is held on the rising edge of ENC+. to 1/3VDD selects demultiplexed CMOS mode. Connecting Internally biased to 1.6V through a 6.2kΩ resistor. Output LVDS to 2/3VDD selects Low Power LVDS mode. Connect- data can be latched on the rising edge of ENC+. ing LVDS to VDD selects Standard LVDS mode.
ENC– (Pin 13):
Negative Differential Encode Input. The
MODE (Pin 62):
Output Format and Clock Duty Cycle sampled analog input is held on the falling edge of ENC–. Stabilizer Selection Pin. Connecting MODE to 0V selects Internally biased to 1.6V through a 6.2kΩ resistor. By- offset binary output format and disables the clock duty pass to ground with a 0.1μF capacitor for a single-ended cycle stabilizer. Connecting MODE to 1/3VDD selects offset Encode signal. binary output format and enables the clock duty cycle sta- bilizer. Connecting MODE to 2/3V
SHDN (Pin 19):
Power Shutdown Pin. SHDN = low results DD selects 2’s complement output format and enables the clock duty cycle stabilizer. in normal operation. SHDN = high results in powered Connecting MODE to V down analog circuitry and the digital outputs are placed DD selects 2’s complement output format and disables the clock duty cycle stabilizer. in a high impedance state.
RAND (Pin 63):
Digital Output Randomization Selection
DITH (Pin 20):
Internal Dither Enable Pin. DITH = low Pin. RAND low results in normal operation. RAND high disables internal dither. DITH = high enables internal selects D1-D15 to be EXCLUSIVE-ORed with D0 (the dither. Refer to Internal Dither section of this data sheet LSB). The output can be decoded by again applying an for details on dither operation. XOR operation between the LSB and all other bits. This
DB0-DB15 (Pins 21-30 and 33-38):
Digital Outputs, B Bus. mode of operation reduces the effects of digital output DB15 is the MSB. Active in demultiplexed mode. The B bus interference. is in high impedance state in full rate CMOS mode.
NC (Pin 64):
Not Connected Internally. For pin compatibility
OGND (Pins 31 and 50):
Output Driver Ground. with the LTC2208 this pin should be connected to GND or
OV
V
DD (Pins 32 and 49):
Positive Supply for the Output DD as required. Otherwise no connection. Drivers. Bypass to ground with 1μF capacitor.
GND (Exposed Pad):
ADC Power Ground. The exposed
OFB (Pin 39):
Over/Under Flow Digital Output for the B Bus. pad on the bottom of the package must be soldered to OFB is high when an over or under fl ow has occurred on the ground. B bus. At high impedance state in full rate CMOS mode. 2217f 14
PIN FUNCTIONS For CMOS Mode. Full Rate or Demultiplexed CLKOUTB (Pin 40):
Data Valid Output. CLKOUTB will toggle
SENSE (Pin 1):
Reference Mode Select and External at the sample rate in full rate CMOS mode or at 1/2 the Reference Input. Tie SENSE to V sample rate in demultiplexed mode. Latch the data on the DD to select the internal 2.5V bandgap reference. An external reference of 2.5V or falling edge of CLKOUTB. 1.25V may be used; both reference values will set a full
CLKOUTA (Pin 41):
Inverted Data Valid Output. CLKOUTA scale ADC range of 2.75V. will toggle at the sample rate in full rate CMOS mode or
GND (Pins 2, 4, 7, 10, 11, 14, 18):
ADC Power Ground. at 1/2 the sample rate in demultiplexed mode. Latch the data on the rising edge of CLKOUTA.
VCM (Pin 3):
1.575V Output. Optimum voltage for input com- mon mode. Must be bypassed to ground with a minimum
DA0-DA15 (Pins 42-48 and 51-59):
Digital Outputs, A Bus. of 2.2μF. Ceramic chip capacitors are recommended. DA15 is the MSB. Output bus for full rate CMOS mode and demultiplexed mode.
VDD (Pins 5, 6, 15, 16, 17):
3.3V Analog Supply Pin. Bypass to GND with 1μF ceramic chip capacitors.
OFA (Pin 60):
Over/Under Flow Digital Output for the A Bus. OFA is high when an over or under fl ow has occurred
A + IN (Pin 8):
Positive Differential Analog Input. on the A bus.
A – IN (Pin 9):
Negative Differential Analog Input.
LVDS (Pin 61):
Data Output Mode Select Pin. Connecting
ENC+ (Pin 12):
Positive Differential Encode Input. The LVDS to 0V selects full rate CMOS mode. Connecting LVDS sampled analog input is held on the rising edge of ENC+. to 1/3VDD selects demultiplexed CMOS mode. Connecting Internally biased to 1.6V through a 6.2kΩ resistor. Output LVDS to 2/3VDD selects Low Power LVDS mode. Connect- data can be latched on the rising edge of ENC+. ing LVDS to VDD selects Standard LVDS mode.
ENC– (Pin 13):
Negative Differential Encode Input. The
MODE (Pin 62):
Output Format and Clock Duty Cycle sampled analog input is held on the falling edge of ENC–. Stabilizer Selection Pin. Connecting MODE to 0V selects Internally biased to 1.6V through a 6.2kΩ resistor. By- offset binary output format and disables the clock duty pass to ground with a 0.1μF capacitor for a single-ended cycle stabilizer. Connecting MODE to 1/3VDD selects offset Encode signal. binary output format and enables the clock duty cycle sta- bilizer. Connecting MODE to 2/3V
SHDN (Pin 19):
Power Shutdown Pin. SHDN = low results DD selects 2’s complement output format and enables the clock duty cycle stabilizer. in normal operation. SHDN = high results in powered Connecting MODE to V down analog circuitry and the digital outputs are placed DD selects 2’s complement output format and disables the clock duty cycle stabilizer. in a high impedance state.
RAND (Pin 63):
Digital Output Randomization Selection
DITH (Pin 20):
Internal Dither Enable Pin. DITH = low Pin. RAND low results in normal operation. RAND high disables internal dither. DITH = high enables internal selects D1-D15 to be EXCLUSIVE-ORed with D0 (the dither. Refer to Internal Dither section of this data sheet LSB). The output can be decoded by again applying an for details on dither operation. XOR operation between the LSB and all other bits. This
DB0-DB15 (Pins 21-30 and 33-38):
Digital Outputs, B Bus. mode of operation reduces the effects of digital output DB15 is the MSB. Active in demultiplexed mode. The B bus interference. is in high impedance state in full rate CMOS mode.
NC (Pin 64):
Not Connected Internally. For pin compatibility
OGND (Pins 31 and 50):
Output Driver Ground. with the LTC2208 this pin should be connected to GND or
OV
V
DD (Pins 32 and 49):
Positive Supply for the Output DD as required. Otherwise no connection. Drivers. Bypass to ground with 1μF capacitor.
GND (Exposed Pad):
ADC Power Ground. The exposed
OFB (Pin 39):
Over/Under Flow Digital Output for the B Bus. pad on the bottom of the package must be soldered to OFB is high when an over or under fl ow has occurred on the ground. B bus. At high impedance state in full rate CMOS mode. 2217f 14