Datasheet LTC1860L, LTC1861L (Analog Devices) - 8
| 制造商 | Analog Devices |
| 描述 | µPower, 3V, 12-Bit, 150ksps 1- and 2-Channel ADCs in MSOP |
| 页数 / 页 | 12 / 8 — TEST CIRCUITS. Load Circuit for tdDO, tr, tf, tdis and ten. Voltage … |
| 文件格式/大小 | PDF / 240 Kb |
| 文件语言 | 英语 |
TEST CIRCUITS. Load Circuit for tdDO, tr, tf, tdis and ten. Voltage Waveforms for SDO Rise and Fall Times, tr, tf
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文件文字版本
LTC1860L/LTC1861L
TEST CIRCUITS Load Circuit for tdDO, tr, tf, tdis and ten Voltage Waveforms for SDO Rise and Fall Times, tr, tf
TEST POINT VOH SDO V 3k V OL CC tdis WAVEFORM 2, ten SDO tdis WAVEFORM 1 t 20pF r tf 1860 TC04 1860 TC01
Voltage Waveforms for ten Voltage Waveforms for tdis
CONV CONV V SDO IH 1860 TC03 ten SDO 90% WAVEFORM 1 (SEE NOTE 1)
Voltage Waveforms for SDO Delay Times, tdDO and thDO
tdis SDO WAVEFORM 2 10% SCK (SEE NOTE 2) VIL NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH tdDO THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL thDO NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL VOH 1860 TC05 SDO VOL 1860 TC02
U U W U APPLICATIO S I FOR ATIO LTC1860L OPERATION Analog Inputs
The LTC1860L has a unipolar differential analog input. The
Operating Sequence
converter will measure the voltage between the “IN+” and The LTC1860L conversion cycle begins with the rising “IN–” inputs. A zero code will occur when IN+ minus IN– edge of CONV. After a period equal to tCONV, the conver- equals zero. Full scale occurs when IN+ minus IN– equals sion is finished. If CONV is left high after this time, the VREF minus 1LSB. See Figure 2. Both the “IN+” and LTC1860L goes into sleep mode drawing only leakage “IN–” inputs are sampled at the same time, so common current. On the falling edge of CONV, the LTC1860L goes mode noise on the inputs is rejected by the ADC. If “IN–” into sample mode and SDO is enabled. SCK synchronizes is grounded and VREF is tied to VCC, a rail-to-rail input span the data transfer with each bit being transmitted from SDO will result on “IN+” as shown in Figure 3. on the falling SCK edge. The receiving system should capture the data from SDO on the rising edge of SCK. After
Reference Input
completing the data transfer, if further SCK clocks are The voltage on the reference input of the LTC1860L (and applied with CONV low, SDO will output zeros indefinitely. the LTC1861L MSOP package) defines the full-scale range See Figure 1. of the A/D converter. These ADCs can operate with refer- ence voltages from VCC to 1V. 18601Lf 8
TEST CIRCUITS Load Circuit for tdDO, tr, tf, tdis and ten Voltage Waveforms for SDO Rise and Fall Times, tr, tf
TEST POINT VOH SDO V 3k V OL CC tdis WAVEFORM 2, ten SDO tdis WAVEFORM 1 t 20pF r tf 1860 TC04 1860 TC01
Voltage Waveforms for ten Voltage Waveforms for tdis
CONV CONV V SDO IH 1860 TC03 ten SDO 90% WAVEFORM 1 (SEE NOTE 1)
Voltage Waveforms for SDO Delay Times, tdDO and thDO
tdis SDO WAVEFORM 2 10% SCK (SEE NOTE 2) VIL NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH tdDO THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL thDO NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL VOH 1860 TC05 SDO VOL 1860 TC02
U U W U APPLICATIO S I FOR ATIO LTC1860L OPERATION Analog Inputs
The LTC1860L has a unipolar differential analog input. The
Operating Sequence
converter will measure the voltage between the “IN+” and The LTC1860L conversion cycle begins with the rising “IN–” inputs. A zero code will occur when IN+ minus IN– edge of CONV. After a period equal to tCONV, the conver- equals zero. Full scale occurs when IN+ minus IN– equals sion is finished. If CONV is left high after this time, the VREF minus 1LSB. See Figure 2. Both the “IN+” and LTC1860L goes into sleep mode drawing only leakage “IN–” inputs are sampled at the same time, so common current. On the falling edge of CONV, the LTC1860L goes mode noise on the inputs is rejected by the ADC. If “IN–” into sample mode and SDO is enabled. SCK synchronizes is grounded and VREF is tied to VCC, a rail-to-rail input span the data transfer with each bit being transmitted from SDO will result on “IN+” as shown in Figure 3. on the falling SCK edge. The receiving system should capture the data from SDO on the rising edge of SCK. After
Reference Input
completing the data transfer, if further SCK clocks are The voltage on the reference input of the LTC1860L (and applied with CONV low, SDO will output zeros indefinitely. the LTC1861L MSOP package) defines the full-scale range See Figure 1. of the A/D converter. These ADCs can operate with refer- ence voltages from VCC to 1V. 18601Lf 8