Datasheet LTC1411 (Analog Devices)

制造商Analog Devices
描述Single Supply 14-Bit 2.5Msps ADC
页数 / 页16 / 1 — FEATURES. DESCRIPTIO. Sample Rate: 2.5Msps. 80dB S/(N + D) and 90dB THD …
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FEATURES. DESCRIPTIO. Sample Rate: 2.5Msps. 80dB S/(N + D) and 90dB THD at 100kHz f. Single 5V Operation. No Pipeline Delay

Datasheet LTC1411 Analog Devices

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LTC1411 Single Supply 14-Bit 2.5Msps ADC
U FEATURES DESCRIPTIO

Sample Rate: 2.5Msps
The LTC ®1411 is a 2.5Msps sampling 14-bit A/D con- ■
80dB S/(N + D) and 90dB THD at 100kHz f
verter in a 36-pin SSOP package, which typically dissi-
IN

Single 5V Operation
pates only 195mW from a single 5V supply. This device ■
No Pipeline Delay
comes complete with a high bandwidth sample-and- ■
Programmable Input Ranges
hold, a precision reference, programmable input ranges ■ Low Power Dissipation: 195mW (Typ) and an internally trimmed clock. The ADC can be powered ■ True Differential Inputs Reject Common Mode Noise down with either the Nap or Sleep mode for low power ■ Out-of-Range Indicator applications. ■ Internal or External Reference The LTC1411 converts either differential or single-ended ■ Sleep (1µA) and Nap (2mA) Shutdown Modes inputs and presents data in 2’s complement format. ■ 36-Pin SSOP Package Maximum DC specs include ±2LSB INL and 14-bit no
U
missing code over temperature. Outstanding dynamic
APPLICATIO S
performance includes 80dB S/(N + D) and 90dB THD at 100kHz input frequency. ■ Telecommunications ■ High Speed Data Acquisition The LTC1411 has four programmable input ranges se- ■ Digital Signal Processing lected by two digital input pins, PGA0 and PGA1. This ■ Multiplexed Data Acquisition Systems provides input spans of ±1.8V, ±1.27V, ±0.9V and ±0.64V. ■ Spectrum Analysis An out-of-the-range signal together with the D13 (MSB) ■ Imaging Systems will indicate whether a signal is over or under the ADC’s input range. A simple conversion start input and a data , LTC and LT are registered trademarks of Linear Technology Corporation. ready signal ease connections to FIFOs, DSPs and micro- processors.
W BLOCK DIAGRA
10 30 AVP DVP OV + DD A
S/(N + D) and Effective Bits
IN 29 1
vs Input Frequency
A – IN OGND 28 2 86 14 D13 80 13 2.5V 12 REFOUT 74 12 3 BANDGAP + 14-BIT REFERENCE 14 68 11 ADC REFIN – • EFFECTIVE BITS 62 10 4 • 56 5k OUTPUT • 50 DRIVERS 44 5k 2k D0 25 S/(N + D) (dB) 38 INTERNAL BUSY REFCOM1 CLOCK 27 32 5 OTR 26 26 20 REFCOM2 X1.62/ 6 CONTROL LOGIC 14 X1.15 10 100 1000 10000 INPUT FREQUENCY (kHz) 1411 TA02 7, 8, 9 AGND AVM SLP NAP PGA0 PGA1 CONVST DGND 1411 BD 11 36 35 34 33 32 31 1411f 1