Datasheet AD847 (Analog Devices) - 11

AD847 OFFSET NULLING +VS
The input offset voltage of the AD847 is very low for a high speed op amp, but if additional nulling is required, the circuit shown in Figure 21 can be used.
C F OUTPUT –IN +IN –V
Figure 21. Offset Nulling
S NULL 1 NULL 8 INPUT CONSIDERATIONS
An input resistor (RIN in Figure 20) is required in circuits where Figure 22. AD847 Simplified Schematic the input to the AD847 will be subjected to transient or con- tinuous overload voltages exceeding the ± 6 V maximum differ-
GROUNDING AND BYPASSING
ential limit. This resistor provides protection for the input In designing practical circuits with the AD847, the user must transistors by limiting the maximum current that can be forced remember that whenever high frequencies are involved, some into their bases. special precautions are in order. Circuits must be built with For high performance circuits it is recommended that a resistor short interconnect leads. A large ground plane should be used (R whenever possible to provide a low resistance, low inductance B in Figures 19 and 20) be used to reduce bias current errors by matching the impedance at each input. The offset voltage er- circuit path, as well as minimizing the effects of high frequency ror will be reduced by more than an order of magnitude. coupling. Sockets should be avoided because the increased interlead capacitance can degrade bandwidth.
THEORY OF OPERATION
Feedback resistors should be of low enough value to assure that The AD847 is fabricated on Analog Devices’ proprietary the time constant formed with the capacitance at the amplifier complementary bipolar (CB) process which enables the con- summing junction will not limit the amplifier performance. struction of pnp and npn transistors with similar fTs in the Resistor values of less than 5 kΩ are recommended. If a larger 600 MHz to 800 MHz region. The AD847 circuit (Figure 22) resistor must be used, a small (<10 pF) feedback capacitor in includes an npn input stage followed by fast pnps in the folded parallel with the feedback resistor, RF, may be used to compen- cascode intermediate gain stage. The CB pnps are also used in sate for the input capacitances and optimize the dynamic perfor- the current amplifying output stage. The internal compensation mance of the amplifier. capacitance that makes the AD847 unity gain stable is provided Power supply leads should be bypassed to ground as close as by the junction capacitances of transistors in the gain stage. possible to the amplifier pins. Ceramic disc capacitors of The capacitor, CF, in the output stage mitigates the effect of ca- 0.1 µF are recommended. pacitive loads. At low frequencies and with low capacitive loads, the gain from the compensation node to the output is very close to unity. In this case CF is bootstrapped and does not contribute to the compensation capacitance of the part. As the capacitive load is increased, a pole is formed with the output impedance of the output stage. This reduces the gain, and therefore, CF is incompletely bootstrapped. Some fraction of CF contributes to the compensation capacitance, and the unity gain bandwidth falls. As the load capacitance is increased, the band- width continues to fall, and the amplifier remains stable. REV. F –9–