Datasheet MCP6001, MCP6001R, MCP6001U, MCP6002, MCP6004 (Microchip) - 19

MCP6001/1R/1U/2/4 6.0 PACKAGING INFORMATION 6.1 Package Marking Information
5-Lead SC-70 (
MCP6001
) Example: (I-Temp) XXN (Front)
I-Temp E-Temp Device
AA7 (Front) YWW (Back)
Code Code
432 (Back) MCP6001 AAN CDN
Note:
Applies to 5-Lead SC-70.
OR OR I-Temp E-Temp Device
XXNN
Code Code
AA74 MCP6001 AANN CDNN
Note:
Applies to 5-Lead SC-70. 5-Lead SOT-23 (
MCP6001/1R/1U
) Example: (E-Temp) 5 4
I-Temp E-Temp
5 4
Device Code Code
XXNN MCP6001 AANN CDNN CD25 MCP6001R ADNN CENN 1 2 3 MCP6001U AFNN CFNN 1 2 3
Note:
Applies to 5-Lead SOT-23. 8-Lead PDIP (300 mil) Example: XXXXXXXX
MCP6002 MCP6002
XXXXXNNN I/P256 I/P^^2 e 56
OR
3 YYWW 0432 0746 8-Lead DFN (2 x 3) Example: XXX ABY YWW 944 NN 25
Legend:
XX...X Customer-specific information Y Year code (last digit of calendar year) YY Year code (last 2 digits of calendar year) WW Week code (week of January 1 is week ‘01’) NNN Alphanumeric traceability code e3 Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator ( ) e3 can be found on the outer packaging for this package.
Note
: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. DS21733J-page 19 Document Outline 1.0 Electrical Characteristics 1.1 Test Circuits FIGURE 1-1: AC and DC Test Circuit for Most Specifications. 2.0 Typical Performance Curves FIGURE 2-1: Input Offset Voltage. FIGURE 2-2: Input Offset Voltage Drift. FIGURE 2-3: Input Offset Quadratic Temp. Co. FIGURE 2-4: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 1.8V. FIGURE 2-5: Input Offset Voltage vs. Common Mode Input Voltage at VDD = 5.5V. FIGURE 2-6: Input Offset Voltage vs. Output Voltage. FIGURE 2-7: Input Bias Current at +85°C. FIGURE 2-8: Input Bias Current at +125°C. FIGURE 2-9: CMRR, PSRR vs. Ambient Temperature. FIGURE 2-10: PSRR, CMRR vs. Frequency. FIGURE 2-11: Open-Loop Gain, Phase vs. Frequency. FIGURE 2-12: Input Noise Voltage Density vs. Frequency. FIGURE 2-13: Output Short Circuit Current vs. Power Supply Voltage. FIGURE 2-14: Output Voltage Headroom vs. Output Current Magnitude. FIGURE 2-15: Quiescent Current vs. Power Supply Voltage. FIGURE 2-16: Small-Signal, Non-Inverting Pulse Response. FIGURE 2-17: Large-Signal, Non-Inverting Pulse Response. FIGURE 2-18: Slew Rate vs. Ambient Temperature. FIGURE 2-19: Output Voltage Swing vs. Frequency. FIGURE 2-20: Measured Input Current vs. Input Voltage (below VSS). FIGURE 2-21: The MCP6001/2/4 Show No Phase Reversal. 3.0 Pin Descriptions TABLE 3-1: Pin Function Table 3.1 Analog Outputs 3.2 Analog Inputs 3.3 Power Supply Pins 3.4 Exposed Thermal Pad (EP) 4.0 Application Information 4.1 Rail-to-Rail Inputs FIGURE 4-1: Simplified Analog Input ESD Structures. FIGURE 4-2: Protecting the Analog Inputs. 4.2 Rail-to-Rail Output 4.3 Capacitive Loads FIGURE 4-3: Output resistor, RISO stabilizes large capacitive loads. FIGURE 4-4: Recommended RISO values for Capacitive Loads. 4.4 Supply Bypass 4.5 Unused Op Amps FIGURE 4-5: Unused Op Amps. 4.6 PCB Surface Leakage FIGURE 4-6: Example Guard Ring Layout for Inverting Gain. 4.7 Application Circuits FIGURE 4-7: Instrumentation Amplifier with Unity-Gain Buffer Inputs. FIGURE 4-8: Active Second-Order Low-Pass Filter. FIGURE 4-9: Peak Detector with Clear and Sample CMOS Analog Switches. 5.0 Design AIDS 5.1 SPICE Macro Model 5.2 FilterLab® Software 5.3 Mindi™ Circuit Designer & Simulator 5.4 Microchip Advanced Part Selector (MAPS) 5.5 Analog Demonstration and Evaluation Boards 5.6 Application Notes 6.0 Packaging Information 6.1 Package Marking Information