Datasheet ADA4530-1 (Analog Devices) - 43

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ADA4530-1 Data Sheet LAYOUT GUIDELINES PHYSICAL IMPLEMENTATION OF GUARDING
impedance insulation. A gap of 15 mil between the A trace and
TECHNIQUES
the guard ring is sufficient. In the Guarding section, guarding was introduced as a tech- Another simplified layout demonstrates the implementation of nique fundamental to high impedance work. The goal of a guard ring in the TIA circuit (see Figure 122). The guard ring guarding is to completely surround the insulation of high is implemented in the same manner as the buffer circuit. The impedance node with another conductor that is driven to the primary difference is that the left half of the feedback resistor guard voltage. This ideal is impossible to achieve in practice; (RF) and feedback capacitor (CF) are connected to the high however, there are several practical structures that provide good impedance node. The guard ring shape is extended around performance. these passive components to ensure that the entire high impedance node is surrounded by guard. The guard ring is
GUARD RING
directly driven from the ADA4530-1 guard buffer (Pin 7). A guard ring is a structure typically used to implement the guarding technique on the surface of the PCB. A simplified layout of the buffer circuit implements the guard ring around
CF
the high impedance (A) trace (see Figure 121). The output of the voltage sensor is wired directly to the A and B pads in Figure 121. The guard ring is a filled copper shape that
RF VOUT
completely surrounds the high impedance (A) trace from the sensor connection to the noninverting input (Pin 1). The guard ring is driven directly from the ADA4530-1 guard buffer (Pin 2)
V+
through a thermal relief shape connection. It is not necessary to
A
connect the other guard buffer output (Pin 7).
C+ GUARD
The solder mask was removed from the high impedance trace
GND
and the guard trace to ensure that the guard makes electrical
ADA4530-1
contact with any surface leakage paths. For the same reason, avoid printing any silkscreen in this section.
C– B V–
1 32 5- 340 1 Figure 122. TIA Circuit Layout
RF VOUT
The guard voltage in the TIA circuit is nominally equal to the B
RS
voltage, which makes it possible to drive the guard ring directly
V+
from the B voltage without using the ADA4530-1 guard buffer.
C+
When implementing the guard ring this way, do not make any connection to the guard buffer outputs (Pin 2 and Pin 7).
B ADA4530-1 GND GUARD PLANE
A guard plane is a structure used to implement the guarding
C–
technique through the bulk of the PCB. The structure of the
A
guard plane is shown in a cross section of the PCB (see Figure 123).
V–
The guard plane is a filled copper shape that is placed directly
GUARD
below the high impedance (A) trace. This plane is connected to the guard ring on the surface layer with vias. -320 405 13 If the circuit board is constructed using high performance PCB Figure 121. Buffer Circuit Layout laminates such as Rogers 4350B, a hybrid stackup is required for There is not a large amount of exposed insulation between the mechanical strength. The outside layers are ceramic, whereas the A trace and the guard ring. It is often counterproductive to core layers are conventional glass epoxy laminate. It is important to increase this spacing to try to increase the insulation resistance place the guard shield on the boundary of the ceramic and glass because the exposed insulator tends to accumulate surface epoxy materials to protect the high impedance node from the charges generated from piezoelectric or triboelectric effects. poor dielectric relaxation characteristics of the glass epoxy These charges are eventually swept across the insulator toward materials. the high impedance conductor. The magnitude of this error current is dependent on the area of the exposed high Rev. A | Page 42 of 50 Document Outline FEATURES APPLICATIONS PIN CONNECTION DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 5 V NOMINAL ELECTRICAL CHARACTERISTICS 10 V NOMINAL ELECTRICAL CHARACTERISTICS 15 V NOMINAL ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS MAIN AMPLIFIER, DC PERFORMANCE MAIN AMPLIFIER, AC PERFORMANCE GUARD AMPLIFIER THEORY OF OPERATION ESD STRUCTURE INPUT STAGE GAIN STAGE OUTPUT STAGE GUARD BUFFER APPLICATIONS INFORMATION INPUT PROTECTION SINGLE-SUPPLY AND RAIL-TO-RAIL OUTPUT CAPACITIVE LOAD STABILITY EMI REJECTION RATIO HIGH IMPEDANCE MEASUREMENTS INPUT BIAS CURRENT INPUT RESISTANCE INPUT OFFSET VOLTAGE INSULATION RESISTANCE GUARDING DIELECTRIC RELAXATION HUMIDITY EFFECTS CONTAMINATION CLEANING AND HANDLING SOLDER PASTE SELECTION CURRENT NOISE CONSIDERATIONS LAYOUT GUIDELINES PHYSICAL IMPLEMENTATION OF GUARDING TECHNIQUES GUARD RING GUARD PLANE VIA FENCE CABLES AND CONNECTORS ELECTROSTATIC INTERFERANCE PHOTODIODE INTERFACE DC ERROR ANALYSIS AC ERROR ANALYSIS NOISE ANALYSIS DESIGN RECOMMENDATIONS DESIGN EXAMPLE POWER SUPPLY RECOMMENDATIONS POWER SUPPLY CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE