SHARC
Embedded Processor
ADSP-21261/ADSP-21262/ADSP-21266
SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high performance audio processing
Code compatibility—at assembly level, uses the same
instruction set as other SHARC DSPs
Processes high performance audio while enabling low
system costs
Audio decoders and postprocessor algorithms support
nonvolatile memory that can be configured to contain a
combination of PCM 96 kHz, Dolby Digital, Dolby Digital
Surround EX, DTS-ES Discrete 6.1, DTS-ES Matrix 6.1, DTS
96/24 5.1, MPEG2 AAC LC, MPEG2 BC 2ch, WMAPRO V7.1, Dolby Pro Logic II, Dolby Pro Logic 2x, and
DTS Neo:6
Various multichannel surround sound decoders are contained in ROM. For configurations of decoder algorithms,
see Table 3 on Page 4. Single-instruction multiple-data (SIMD) computational architecture—two 32-bit IEEE floating-point/32-bit fixed-point/
40-bit extended precision floating-point computational
units, each with a multiplier, ALU, shifter, and register file
High bandwidth I/O—a parallel port, an SPI port, 6 serial
ports, a Digital application interface (DAI), and JTAG
DAI incorporates two precision clock generators (PCGs), an …