Datasheet Texas Instruments DAC5687IPZP — 数据表

制造商Texas Instruments
系列DAC5687
零件号DAC5687IPZP
Datasheet Texas Instruments DAC5687IPZP

双通道,16位,500MSPS,1x-8x内插数模转换器(DAC)100-HTQFP -40至85

数据表

16-Bit 500 MSPS 2x-8x Interpolating Dual-Channel DAC datasheet
PDF, 2.7 Mb, 修订版: E, 档案已发布: Sep 20, 2006
从文件中提取

价格

状态

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityYes

打包

Pin100
Package TypePZP
Industry STD TermHTQFP
JEDEC CodeS-PQFP-G
Package QTY90
CarrierEIAJ TRAY (10+1)
Device MarkingDAC5687IPZP
Width (mm)14
Length (mm)14
Thickness (mm)1
Pitch (mm).5
Max Height (mm)1.2
Mechanical Data下载

参数化

ArchitectureCurrent Sink
DAC Channels2
InterfaceParallel CMOS
Interpolation1x,2x,4x,8x
Operating Temperature Range-40 to 85 C
Package GroupHTQFP
Package Size: mm2:W x L100HTQFP: 256 mm2: 16 x 16(HTQFP) PKG
Power Consumption(Typ)1410 mW
RatingCatalog
Resolution16 Bits
SFDR80 dB
Sample / Update Rate500 MSPS

生态计划

RoHSCompliant

设计套件和评估模块

  • Evaluation Modules & Boards: DAC5687EVM
    DAC5687 Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)
  • Evaluation Modules & Boards: TRF3703-17EVM
    TRF3703-17 Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)
  • Evaluation Modules & Boards: TSW3100EVM
    TSW3100 Pattern Generator Module
    Lifecycle Status: Obsolete (Manufacturer has discontinued the production of the device)
  • Evaluation Modules & Boards: DAC5688EVM
    DAC5688 Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)
  • Evaluation Modules & Boards: TSW2200EVM
    TSW2200 Low-Cost Portable Power Supply Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)

应用须知

  • DAC5686/DAC5687 Clock Generation Using PLL & External Clock Modes (Rev. A)
    PDF, 686 Kb, 修订版: A, 档案已发布: Jul 21, 2005
    DAC5686/DAC5687 Application NOte Clock Generation Using PLL & External Clock Modes
  • Interfacing op amps to high-speed DACs, Part 1: Current-sinking DACs
    PDF, 319 Kb, 档案已发布: Jul 14, 2009
  • Passive Terminations for Current Output DACs
    PDF, 244 Kb, 档案已发布: Nov 10, 2008
    The correct implementation of the high-speed DAC output termination is critical to achieving the best possible performance. The typical application involves choosing the correct network to create the necessary dc bias levels and correct effective impedance load to keep the output voltage within the compliance levels. This ensures that the maximum output signal amplitude and optimum ac performance
  • Q3 2009 Issue Analog Applications Journal
    PDF, 2.1 Mb, 档案已发布: Jul 14, 2009
  • High Speed Digital-to-Analog Converters Basics (Rev. A)
    PDF, 829 Kb, 修订版: A, 档案已发布: Oct 23, 2012
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, 档案已发布: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers

模型线

系列: DAC5687 (3)

制造商分类

  • Semiconductors > Data Converters > Digital-to-Analog Converters (DACs) > High Speed DACs (>10MSPS)