SN74SSQEC32882
SCAS920-PUB – NOVEMBER 2011 www.ti.com 28-Bit to 56-Bit Registered Buffer With Address Parity Test
One Pair to Four Pair Differential Clock PLL Driver
Check for Samples: SN74SSQEC32882 FEATURES 1 JEDEC SSTE32882
1-to-2 Register Outputs and 1-to-4 Clock Pair
Outputs Support Stacked DDR3 RDIMMs
CKE Powerdown Mode for Optimized System
Power Consumption
1.5V/1.35V/1.25V Phase Lock Loop Clock
Driver for Buffering One Differential Clock Pair
(CK and CK) and Distributing to Four
Differential Outputs
1.5V/1.35V/1.25V CMOS Inputs
Checks Parity on Command and Address (CS-Gated) Data Inputs
Configurable Driver Strength
Uses Internal Feedback Loop
Optimized Power Consumption APPLICATIONS DDR3 Registered DIMMs up to DDR3-1866
DDR3L Registered DIMMs up to DDR3L-1600
DDR3U Registered DIMMs up to DDR3U-1333
Single-, Dual-and Quad-Rank RDIMM DESCRIPTION
This 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3
registered DIMMs with VDD of 1.5 V, on DDR3L registered DIMMs with VDD of 1.35 V and on DDR3U registered
DIMMs with VDD of 1.25 V. …
