Datasheet Texas Instruments CDCVF2509APWRG4 — 数据表
| 制造商 | Texas Instruments |
| 系列 | CDCVF2509A |
| 零件号 | CDCVF2509APWRG4 |
具有掉电功能的3.3V锁相环时钟驱动器24-TSSOP 0至85
数据表
3.3-V Phase-Lock Look Clock Driver With Power Down Mode datasheet
PDF, 746 Kb, 修订版: E, 档案已发布: Feb 25, 2010
从文件中提取
价格
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
打包
| Pin | 24 |
| Package Type | PW |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Device Marking | CKV2509A |
| Width (mm) | 4.4 |
| Length (mm) | 7.8 |
| Thickness (mm) | 1 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | 下载 |
参数化
| Absolute Jitter (Peak-to-Peak Cycle or Period Jitter) | 125 ps |
| Function | SDR |
| Number of Outputs | 9 |
| Operating Frequency Range(Max) | 175 MHz |
| Operating Frequency Range(Min) | 20 MHz |
| Operating Temperature Range | 0 to 85 C |
| Output Drive | 12 mA |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP) PKG |
| Rating | Catalog |
| VCC | 3.3 V |
| t(phase error) | 50 ps |
| tsk(o) | 100 ps |
生态计划
| RoHS | Compliant |
应用须知
- Generating Early Clock using TI's CDCVF2509/CDCVF2510 PLLsPDF, 68 Kb, 档案已发布: Jul 23, 2004
模型线
系列: CDCVF2509A (4)
- CDCVF2509APW CDCVF2509APWG4 CDCVF2509APWR CDCVF2509APWRG4
制造商分类
- Semiconductors > Clock and Timing > Memory Interface Clocks and Registers