Datasheet Texas Instruments CDCVF2505D — 数据表
制造商 | Texas Instruments |
系列 | CDCVF2505 |
零件号 | CDCVF2505D |
用于同步的PLL时钟驱动器。 DRAM&Gen.Purp。具有扩频兼容性的应用,掉电模式8-SOIC -40至85
数据表
CDCVF2505 3.3-V Clock Phase-Lock Loop Clock Driver datasheet
PDF, 1.2 Mb, 修订版: G, 档案已发布: Aug 31, 2016
从文件中提取
价格
状态
Lifecycle Status | Active (Recommended for new designs) |
Manufacture's Sample Availability | Yes |
打包
Pin | 8 |
Package Type | D |
Industry STD Term | SOIC |
JEDEC Code | R-PDSO-G |
Package QTY | 75 |
Carrier | TUBE |
Device Marking | CKV05 |
Width (mm) | 3.91 |
Length (mm) | 4.9 |
Thickness (mm) | 1.58 |
Pitch (mm) | 1.27 |
Max Height (mm) | 1.75 |
Mechanical Data | 下载 |
参数化
Absolute Jitter (Peak-to-Peak Cycle or Period Jitter) | 150 ps |
Function | SDR |
Number of Outputs | 4 |
Operating Frequency Range(Max) | 200 MHz |
Operating Frequency Range(Min) | 24 MHz |
Operating Temperature Range | -40 to 85 C |
Output Drive | 12 mA |
Package Group | SOIC |
Package Size: mm2:W x L | 8SOIC: 29 mm2: 6 x 4.9(SOIC) PKG |
Rating | Catalog |
VCC | 3.3 V |
t(phase error) | 150 ps |
tsk(o) | 150 ps |
生态计划
RoHS | Compliant |
应用须知
- Design and Layout Guidelines for the CDCVF2505 Clock DriverPDF, 176 Kb, 档案已发布: Nov 16, 2000
This application note describes tuning techniques, line termination methods, and filter circuit for the CDCVF2505, and it provides PCB layout guidelines.
模型线
系列: CDCVF2505 (9)
制造商分类
- Semiconductors > Clock and Timing > Memory Interface Clocks and Registers