Datasheet Microchip PL123-09 — 数据表

PL123-05/-09
Low Skew Zero Delay Buffer
FEATURES DESCRIPTION п‚ п‚ The PL123-05/-09 (-05H/-09H for High Drive) are high
performance, low skew, low jitter zero delay buffers
designed to distribute high speed clocks. They have
one (PL123-05) or two (PL123-09) low-skew output
banks, of 4 outputs each, that are synchronized with
the input. The PL123-09 allows control of the banks of
outputs by using the S1 and S2 inputs as shown in the
Selector Definition table on page 2. п‚ п‚ п‚ п‚ п‚ Frequency Range 10MHz to 134 MHz
Output Options:
o 5 outputs PL123-05
o 9 outputs PL123-09
Zero input -output delay
Optional Drive Strength:
Standard (8mA) PL123-05/-09
High (12mA) PL123-05H/-09H
3.3V, В±10% operation
Available in Commercial and Industrial temperature
ranges
Available in 16-Pin SOP or TSSOP (PL123-09),
and 8-Pin SOP (PL123-05) packages The synchronization is established via CLKOUT feed
back to the input of the PLL. Since the skew between …