DATASHEET
CD4030BMS FN3305
Rev 0.00
December 1992 CMOS Quad Exclusive-OR Gate Features Pinout High Voltage Type (20V Rating) CD4030BMS
TOP VIEW Medium-Speed Operation
-tPHL, tPLH = 65ns (typ) at VDD = 10V, CL = 50pF 100% Tested for Quiescent Current at 20V A 1 14 VDD Standardized Symmetrical Output Characteristics B 2 13 H 5V, 10V and 15V Parametric Ratings J=Aпѓ…B 3 12 G Maximum Input Current Of 1пЃA at 18V Over Full
Package-Temperature Range;
-100nA at 18V and +25oC K=Cпѓ…D 4 11 M = G пѓ… H Noise Margin (Over Full Package Temperature Range):
-1V at VDD = 5V
-2V at VDD = 10V
-2.5V at VDD = 15V Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
�B’ Series CMOS Devices” Applications Even and Odd-Parity Generators and Checkers Logical Comparators Adders/Subtractors C 5 10 L = E  F D 6 9 F 8 E VSS 7 Functional Diagram
1
2 3 5
6 4 8
9 10 12
G
H 13 11 A
B
C
D J K General Logic Functions Description
The CD4030BMS types consist of four independent Exclusive-OR gates. The CD4030BMS provides the system …
