Datasheet Intersil HCS86DMSR — 数据表

DATASHEET
HCS86MS FN3058
Rev 1.00
September 1995 Radiation Hardened Quad 2-Input Exclusive OR Gate Features Pinouts 3 Micron Radiation Hardened SOS CMOS 14 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-183S CDIP2-T14, LEAD FINISH C
TOP VIEW Total Dose 200K RAD (Si) SEP Effective LET No Upsets: >100 MEV-cm2/mg Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/
Bit-Day (Typ) Dose Rate Survivability: >1 x 1012 RAD (Si)/s Dose Rate Upset >10 10 RAD (Si)/s 20ns Pulse Latch-Up Free Under Any Conditions Military Temperature Range: -55oC to +125oC Significant Power Reduction Compared to LSTTL ICs A1 1 14 VCC B1 2 13 B4 Y1 3 12 A4 A2 4 11 Y4 B2 5 10 B3 Y2 6 9 A3 GND 7 8 Y3 DC Operating Voltage Range: 4.5V to 5.5V Input Logic Levels
-VIL = 30% of VCC Max
-VIH = 70% of VCC Min 14 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-183S CDFP3-F14, LEAD FINISH C
TOP VIEW Input Current Levels Ii п‚Ј 5пЃ­A at VOL, VOH Description
The Intersil HCS86MS is a Radiation Hardened Quad 2Input Exclusive OR Gate. A high on any one input exclusively will change the output to a High state.
The HCS86MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family
with either TTL or CMOS input compatibility.
The HCS86MS is supplied in a 14 lead Weld Seal Ceramic
flatpack (K suffix) or a Weld Seal Ceramic Dual-In-Line
Package (D suffix). A1 1 14 VCC B1 2 13 B4 Y1 3 12 A4 A2 4 11 Y4 B2 5 10 B3 Y2 6 9 A3 GND 7 8 Y3 Functional Diagram
(1, 4, 9, 12)
An …