Datasheet Intersil ACS374KMSR — 数据表

DATASHEET
ACS374MS FN3997
Rev 0.00
April 1995 Radiation HardenedOctal D Flip-Flop, Three-State Features Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR CDIP2-T20, LEAD FINISH C
TOP VIEW 1.25 Micron Radiation Hardened SOS CMOS Total Dose 300K RAD (Si) Single Event Upset (SEU) Immunity
80 MEV-cm2/mg Dose Rate Upset >1011 RAD (Si)/s, 20ns Pulse Latch-Up Free Under Any Conditions
o o Military Temperature Range: -55 C to +125 C Significant Power Reduction Compared to ALSTTL Logic DC Operating Voltage Range: 4.5V to 5.5V Input Logic Levels
-VIL = 30% of VCC Max OE 1 Q0 2 19 Q7 D0 3 18 D7 20 VCC D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 CP 20 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR CDFP4-F20, LEAD FINISH C
TOP VIEW -VIH = 70% of VCC Min Input Current п‚Ј1пЃ­A at VOL, VOH Description
The Intersil ACS374MS is a radiation hardened octal D-type
flip-flop with three-state outputs. The eight edge-triggered flipflops enter data into their registers on the low to high transition
of clock (CP). The Output Enable (OEN) controls the three-state
outputs and is independent of the register operation. When the
OEN is high, the outputs will be in the high impedance state.
The ACS374MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of the
radiation hardened, high-speed, CMOS/SOS Logic Family. OE 1 20 VCC Q0 2 19 Q7 D0 3 18 D7 D1 4 17 D6 Q1 5 16 Q6 Q2 6 15 Q5 D2 7 14 D5 D3 8 13 D4 Q3 9 12 Q4 10 11 CP GND Ordering Information
PART NUMBER TEMPERATURE RANGE ACS374DMSR -55oC to +125oC ACS374KMSR -55oC to +125oC SCREENING LEVEL PACKAGE Intersil Class S Equivalent 20 Lead SBDIP Intersil Class S Equivalent 20 Lead Ceramic Flatpack ACS374D/Sample +25oC Sample 20 Lead SBDIP ACS374K/Sample +25oC Sample 20 Lead Ceramic Flatpack ACS374HMSR +25oC Die Die Truth Table Functional Diagram
INPUTS OE CP L
L OUTPUTS …