Datasheet Intersil HCS163KMSR — 数据表

DATASHEET
HCS163MS FN3087
Rev 1.00
September 1995 Radiation Hardened Synchronous Presettable Counter Features Pinouts 3 Micron Radiation Hardened CMOS SOS 16 LEAD CERAMIC DUAL-IN-LINE
METAL SEAL PACKAGE (SBDIP)
MIL-STD-1835 CDIP2-T16, LEAD FINISH C
TOP VIEW Total Dose 200K RAD (Si) SEP Effective LET No Upsets: >100 MEV-cm2/mg Single Event Upset (SEU) Immunity < 2 x 10-9 Errors/
Bit-Day (Typ) Dose Rate Survivability: >1 x 1012 MR 1 16 VCC CP 2 15 TC P0 3 14 Q0 P1 4 13 Q1 P2 5 12 Q2 P3 6 11 Q3 PE 7 10 TE RAD (Si)/s Dose Rate Upset: >1010 RAD (Si)/s 20ns Pulse Latch-Up Free Under Any Conditions Military Temperature Range: -55oC to +125oC Significant Power Reduction Compared to LSTTL ICs 9 GND 8 SPE DC Operating Voltage Range: 4.5V to 5.5V Input Logic Levels
-VIL = 30% of VCC
-VIH = 70% of VCC 16 LEAD CERAMIC METAL SEAL
FLATPACK PACKAGE (FLATPACK)
MIL-STD-1835 CDFP4-F16, LEAD FINISH C
TOP VIEW Input Current Levels Ii п‚Ј 5пЃ­A at VOL, VOH Description
The Intersil HCS163MS is a Radiation Hardened
synchronous presettable binary counter that features lookahead carry logic for use in high speed counting applications.
Counting and parallel load, and presetting are all accomplished synchronously with the positive transition of the
clock.
The HCS163MS utilizes advanced CMOS/SOS technology
to achieve high-speed operation. This device is a member of
radiation hardened, high-speed, CMOS/SOS Logic Family. MR 1 16 VCC CP 2 15 TC P0 3 14 Q0 P1 4 13 Q1 P2 5 12 Q2 P3 6 11 Q3 PE 7 10 TE GND 8 9 SPE The HCS163MS is supplied in a 16 lead Ceramic flatpack (K suf fix) or a SBDIP Package (D suffix). Ordering Information
PART NUMBER TEMPERATURE RANGE SCREENING LEVEL PACKAGE HCS163DMSR -55oC to +125oC Intersil Class S Equivalent 16 Lead SBDIP HCS163KMSR -55oC to +125oC Intersil Class S Equivalent 16 Lead Ceramic Flatpack +25oC Sample 16 Lead SBDIP HCS163K/Sample +25oC Sample 16 Lead Ceramic Flatpack HCS163HMSR +25oC Die Die DB NA HCS163D/Sample FN3087 Rev 1.00
September 1995 Page 1 of 9 HCS163MS Functional Block Diagram
P0 P1 3 P2 4 P3 5 Q0 Q1 Q2 Q3 6 7 …