Datasheet Intersil CD40193BDMSR — 数据表

DATASHEET
CD40192BMS, CD40193BMS FN3363
Rev 0.00
December 1992 CMOS Presettable Up/Down Counters(Dual Clock With Reset) Features Description CD40192BMS -BCD Type CD40192BMS Presettable BCD Up/Down Counter and the
CD40193BMS Presettable Binary Up/Down Counter each consist of 4 synchronously clocked, gated “D” type flip-flops connected as a counter. The inputs consist of 4 individual jam lines,
a PRESET ENABLE control, individual CLOCK UP and
CLOCK DOWN signals and a master RESET. Four buffered Q
signal outputs as well as CARRY and BORROW outputs for
multiple-stage counting schemes are provided. CD40193BMS -Binary Type High Voltage Type (20V Rating) Individual Clock Lines for Counting Up or Counting
Down Synchronous High-Speed Carry and Borrow Propagation Delays for Cascading Asynchronous Reset and Preset Capability Medium Speed Operation
-fCL = 8MHz (typ.) at 10V 5V, 10V and 15V Parametric Ratings Standardize Symmetrical Output Characteristics 100% Tested for Quiescent Current at 20V Maximum Input Current of 1пЃ­A at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC Noise Margin (Over Full Package/Temperature Range)
-1V at VDD = 5V
-2V at VDD = 10V
-2.5V at VDD = 15V Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
�B’ Series CMOS Devices” Applications Up/Down Difference Counting The counter is cleared so that all outputs are in a low state by a
high on the RESET line. A RESET is accomplished asynchronously with the clock. Each output is individually programmable
asynchronously with the clock to the level on the corresponding
jam input when the PRESET ENABLE control is low.
The counter counts up one count on the positive clock edge of
the CLOCK UP signal provided the CLOCK DOWN line is high.
The counter counts down one count on the positive clock edge
of the CLOCK DOWN signal provided the CLOCK UP line is …