Datasheet Intersil CD4029BDMSR — 数据表

DATASHEET
CD4029BMS FN3304
Rev 0.00
December 1992 CMOS Presettable Up/Down Counter Features Description High-Voltage Type (20V Rating) CD4029BMS consists of a four-stage binary or BCD-decade up/
down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN
(CLOCK ENABLE), BINARY/DECADE, UP/DOWN, PRESET
ENABLE, and four individual JAM signals. Q1, Q2, Q3, Q4 and a
CARRY OUT signal are provided as outputs. Medium Speed Operation: 8MHz (Typ.) at CL = 50pF
and VDD -VSS = 10V Multi-Package Parallel Clocking for Synchronous High
Speed Output Response or Ripple Clocking for Slow
Clock Input Rise and Fall Times “Preset Enable” and Individual “Jam” Inputs Provided Binary or Decade Up/Down Counting BCD Outputs in Decade Mode 100% Tested for Maximum Quiescent Current at 20V 5V, 10V and 15V Parametric Ratings Standardized Symmetrical Output Characteristics Maximum Input Current of 1A at 18V Over Full Package-Temperature Range; 100nA at 18V and +25oC Noise Margin (Over Full Package Temperature Range):
-1V at VDD = 5V
-2V at VDD = 10V
-2.5V at VDD = 15V Meets All Requirements of JEDEC Tentative Standards
No. 13B, “Standard Specifications for Description of
“B” Series CMOS Device’s Applications Programmable Binary and Decade Counting/Frequency Synthesizers-BCD Output Analog to Digital and Digital to Analog Conversion Up/Down Binary Counting Difference Counting Magnitude and Sign Generation A high PRESET ENABLE signal allows information on the JAM
INPUTS to preset the counter to any state asynchronously with
the clock. A low on each JAM line, when the PRESET-ENABLE
signal is high, resets the counter to its zero count. The counter is
advanced one count at the positive transition of the clock when
the CARRY-IN and PRE-SET ENABLE signals are low.
Advancement is inhibited when the CARRY-IN or PRESET
ENABLE signals are high. The CARRY-OUT signal is normally …