Datasheet Intersil ACTS161DMSR — 数据表

DATASHEET
ACTS161MS FN4095
Rev.0.00
January 1996 Radiation Hardened 4-Bit Synchronous Counter Features Pinouts Devices QML Qualified in Accordance with MIL-PRF-38535 Detailed Electrical and Screening Requirements are
Contained in SMD# 5962-96716 and Intersil’s QM Plan 16 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835, DESIGNATOR CDIP2-T16,
LEAD FINISH C
TOP VIEW 1.25 Micron Radiation Hardened SOS CMOS
MR 1 16 VCC Single Event Upset (SEU) Immunity: 100 MEV-cm2/mg P1 4 13 Q1 Dose Rate Upset>1011 RAD (Si)/s, 20ns Pulse P2 5 12 Q2 P3 6 11 Q3 PE 7 10 TE Total Dose >300K RAD (Si) Dose Rate Survivability>1012 RAD (Si)/s, 20ns Pulse Latch-Up Free Under Any Conditions 9 SPE GND 8 Military Temperature Range-55oC to +125oC Significant Power Reduction Compared to ALSTTL Logic DC Operating Voltage Range 4.5V to 5.5V 16 PIN CERAMIC FLATPACK
MIL-STD-1835, DESIGNATOR CDFP4-F16,
LEAD FINISH C
TOP VIEW Input Logic Levels
-VIL = 0.8V Max
-VIH = VCC/2 Min Input Current п‚Ј 1пЃ­A at VOL, VOH Fast Propagation Delay25ns (Max), 16ns (Typ) Description
The Intersil ACTS161MS is a Radiation Hardened 4-Bit Binary Synchronous Counter, featuring asynchronous reset and load ahead
carry logic. The MR is an active low master reset. SPE is an active
low Synchronous Parallel Enable which disables counting and
allows data at the preset inputs (P0 -P3) to load the counter. CP is
the positive edge clock. TC is the terminal count or carry output.
Both TE and PE must be high for counting to occur, but are irrelevant to loading. TE low will keep TC low. MR 1 16 VCC CP 2 15 TC P0 3 14 Q0 P1 4 13 Q1 P2 5 12 Q2 P3 6 11 Q3 PE 7 10 TE GND 8 9 SPE The ACTS161MS utilizes advanced CMOS/SOS technology to
achieve high-speed operation. This device is a member of a
radiation hardened, high-speed, CMOS/SOS Logic family.
The ACTS161MS is supplied in a 16 lead Ceramic Flatpack …