Plastic Packages for Integrated Circuits
Thin Shrink Small Outline Exposed Pad Plastic Packages (EPTSSOP)
M28.173A N
INDEX
AREA E 0.25(0.010) M E1 2 L 0.05(0.002)
-A-A D О±
A2
c e A1 b
0.10(0.004) M 0.25
0.010 SEATING PLANE -C-2 SYMBOL 3
TOP VIEW 1 INCHES GAUGE
PLANE -B1 28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE B M 0.10(0.004)
C A M B S 3 MIN MAX MILLIMETERS
MIN MAX NOTES A -0.047 -1.20 -A1 0.002 0.006 0.05 0.15 -A2 0.031 0.051 0.80 1.05 9 b 0.0075 0.0118 0.19 0.30 c 0.0035 0.0079 0.09 0.20 -D 0.378 0.386 9.60 9.80 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC -E 0.246 0.256 6.25 6.50 -L 0.0177 0.0295 0.45 0.75 6 О± 0o 8o 0o 8o -P -0.138 -3.50 11 P1 -0.118 -3.0 11 N 28 28 7 NOTES:
Rev. 1 6/99
1. These package dimensions are within allowable dimensions
of JEDEC MO-153-AET, Issue E.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or
gate burrs. Mold flash, protrusion and gate burrs shall not
exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed …
