Datasheet Intersil X28HC256SM-12T2 — 数据表

DATASHEET
X28HC256 FN8108
Rev 5.00
August 27, 2015 256k, 32k x 8-Bit, 5V, Byte Alterable EEPROM
The X28HC256 is a second generation high performance
CMOS 32k x 8 EEPROM. It is fabricated with Intersil’s
proprietary, textured poly floating gate technology, providing a
highly reliable 5V only nonvolatile memory.
The X28HC256 supports a 128-byte page write operation,
effectively providing a 24Вµs/byte write cycle, and enabling the
entire memory to be typically rewritten in less than 0.8s. The
X28HC256 also features DATA polling and Toggle bit polling,
two methods of providing early end of write detection. The
X28HC256 also supports the JEDEC standard software data
protection feature for protecting against inadvertent writes
during power-up and power-down.
Endurance for the X28HC256 is specified as a minimum
100,000 write cycles per byte and an inherent data retention
of 100 years. Features Access time: 90ns Simple byte and page write
-Single 5V supply
-No external high voltages or VP-P control circuits
-Self timed
-No erase before write …