Datasheet Intersil KAD5512P-50Q72 — 数据表

DATASHEET
KAD5512P-50 FN6805
Rev 4.00
May 31, 2016 12-Bit, 500MSPS A/D Converter Features The KAD5512P-50 is a low-power, high performance, 12-bit,
500MSPS analog-to-digital converter designed with Intersil’s
proprietary FemtoChargeв„ў technology on a standard CMOS
process. The KAD5512P-50 is part of a pin-compatible
portfolio of 10, 12 and 14-bit A/Ds with sample rates ranging
from 125MSPS to 500MSPS. Programmable gain, offset and skew control 1.3GHz analog input bandwidth 60fs clock jitter Over-range indicator The device utilizes two time-interleaved 12-bit, 250MSPS A/D
cores to achieve the ultimate sample rate of 500MSPS. A
single 500MHz conversion clock is presented to the converter,
and all interleave clocking is managed internally. Selectable clock divider: Г 1 or Г 2 Clock phase selection Nap and sleep modes A Serial Peripheral Interface (SPI) port allows for extensive
configurability, as well as fine control of matching
characteristics (gain, offset, skew) between the two converter
cores. These adjustments allow the user to minimize spurs
associated with the interleaving process. Two’s complement, gray code or binary data format Digital output data is presented in selectable LVDS or CMOS
formats. The KAD5512P-50 is available in a 72 Ld QFN
package with an exposed paddle. Performance is specified
across the full industrial temperature range (-40В°C to +85В°C). Pb-free (RoHS compliant) Key Specifications Broadband communications DDR LVDS-compatible or LVCMOS outputs Programmable built-in test patterns Single-supply 1.8V operation Applications Radar and satellite antenna array processing High-performance data acquisition SNR = 65.9dBFS for fIN = 105MHz (-1dBFS) SFDR = 82.0dBc for fIN = 105MHz (-1dBFS) CLKP OVDD CLKDIV AVDD Total power consumption = 432mW CLKOUTP CLOCK GENERATION
AND
INTERLEAVE CONTROL CLKN SHA CLKOUTN 12-BIT
250 MSPS
ADC D[11:0]P …