Precision Receiver Delay Improves Data Transmission
Design Note 129
Victor Fleury
Moving data from one board to another over a backplane
places stringent requirements on channel-to-channel
and part-to-part skew and delay. The propagation delay
of typical CMOS line receivers can vary as much as
500% over process and temperature. In high speed
synchronous systems where clock and data signal
timing are critical, transmission rates must often be
reduced to minimize the effects of propagation delay
and skew uncertainties in the receiver. The LTC В®1518/
LTC1519/LTC1520 family of high speed line receivers solves this problem, reducing propagation delay
changes to less than В±17% over production variations
and temperature, a better than 10 times improvement
over previous solutions.
The LTC1518/LTC1519/LTC1520 family of 50Mbps quad
line receivers translate differential input signals into
CMOS/TTL output logic levels. The receivers employ
a unique architecture that guarantees excellent performance over process and temperature with propagation
delay of 18ns В±3ns. The architecture affords low same
channel skew (|tPHL -tPLH| 500ps typ), and low channelto-channel propagation delay variation (400ps typ). The
propagation delay and skew performance are unmatched …