Datasheet Microchip PIC16F18855T-I/SSVAO — 数据表

PIC16(L)F18855/75
Full-Featured 28/40/44-Pin Microcontrollers
Description
PIC16(L)F18855/75 microcontrollers feature Analog, Core Independent Peripherals and Communication Peripherals,
combined with eXtreme Low-Power (XLP) technology for a wide range of general purpose and low-power applications.
The family will feature the CRC/SCAN, Hardware Limit Timer (HLT) and Windowed Watchdog Timer (WWDT) to support
customers looking to add safety to their application. Additionally, this family includes up to 14 KB of Flash memory, along
with a 10-bit ADC with Computation (ADC2) extensions for automated signal analysis to reduce the complexity of the
application. Core Features Power-Saving Functionality • C Compiler Optimized RISC Architecture
• Only 49 Instructions
• Operating Speed:
-DC – 32 MHz clock input
-125 ns minimum instruction cycle
• Interrupt Capability
• 16-Level Deep Hardware Stack
• Three 8-Bit Timers (TMR2/4/6) with Hardware
Limit Timer (HLT) Extensions
• Four 16-Bit Timers (TMR0/1/3/5)
• Low-Current Power-on Reset (POR)
• Configurable Power-up Timer (PWRTE)
• Brown-out Reset (BOR) with Fast Recovery
• Low-Power BOR (LPBOR) Option
• Windowed Watchdog Timer (WWDT): …

PIC16(L)F18855/75
Full-Featured 28/40/44-Pin Microcontrollers
Description
PIC16(L)F18855/75 microcontrollers feature Analog, Core Independent Peripherals and Communication Peripherals,
combined with eXtreme Low-Power (XLP) technology for a wide range of general purpose and low-power applications.
The family will feature the CRC/SCAN, Hardware Limit Timer (HLT) and Windowed Watchdog Timer (WWDT) to support
customers looking to add safety to their application. Additionally, this family includes up to 14 KB of Flash memory, along
with a 10-bit ADC with Computation (ADC2) extensions for automated signal analysis to reduce the complexity of the
application. Core Features Power-Saving Functionality C Compiler Optimized RISC Architecture Only 49 Instructions Operating Speed:
-DC – 32 MHz clock input
-125 ns minimum instruction cycle Interrupt Capability 16-Level Deep Hardware Stack Three 8-Bit Timers (TMR2/4/6) with Hardware
Limit Timer (HLT) Extensions Four 16-Bit Timers (TMR0/1/3/5) Low-Current Power-on Reset (POR) Configurable Power-up Timer (PWRTE) Brown-out Reset (BOR) with Fast Recovery Low-Power BOR (LPBOR) Option Windowed Watchdog Timer (WWDT):
-Variable prescaler selection
-Variable window size selection
-All sources configurable in hardware or
software Programmable Code Protection DOZE mode: Ability to run the CPU core slower
than the system clock IDLE mode: Ability to halt CPU core while internal
peripherals continue operating Sleep mode: Lowest Power Consumption Peripheral Module Disable (PMD):
-Ability to disable hardware module to
minimize power consumption of unused
peripherals Memory Up to 14 KB Flash Program Memory
Up to 1 KB Data SRAM
256B of EEPROM …