Datasheet Microchip CEC1302D-C0-SZ — 数据表

CEC1302
Low Power Crypto Embedded Controller
Product Features
В® В® ARM Cortex -M4 Processor Core
-32-Bit ARM v7-M Instruction Set Architecture
-Hardware Floating Point Unit (FPU)
-Single 4GByte Addressing Space (Von Neumann Model)
-Little-Endian Byte Ordering
-Bit-Banding Feature Included
-NVIC Nested Vectored Interrupt Controller
-Up to 240 Individually-Vectored Interrupt Sources
Supported
-8 Levels of Priority, Individually Assignable By Vector
-Chip-Level Interrupt Aggregator supported, to
expand number of interrupt sources or reduce
number of vectors -System Tick Timer
-Complete ARM-Standard Debug Support
-JTAG-Based DAP Port, Comprised of SWJ-DP and
AHB-AP Debugger Access Functions
-Full DWT Hardware Functionality: 4 Data
Watchpoints and Execution Monitoring
-Full FPB Hardware Breakpoint Functionality: 6
Execution Breakpoints and 2 Literal (Data) …

CEC1302
CEC1302 ROM Description Addendum INTRODUCTION Audience This document describes the functionality provided by
the ROM code in the CEC1302. This document is written for developers. This document includes the following topics: CEC1302 ROM Design on page 4
Selection of SPI Port on page 4
SPI Load of Firmware on page 5
Load Failures on page 9
ROM Event Log on page 9
SHA-256 Hashing and Data Order on page 11
ROM Runtime API on page 15 пѓЈ 2016 Microchip Technology Inc. References
The following documents should be referenced when
using this addendum. See your Microchip representative for availability. CEC1302 Data Sheet
CEC1302 Crypto API User’s Guide
CEC1302 Peripheral API User’s Guide
CEC1302 CLIB/PLIB Releases DS00002235A-page 1 CEC1302
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