FEATURES FUNCTIONAL BLOCK DIAGRAM Low power, dual 16-bit nanoDAC
Relative accuracy: В±12 LSBs maximum
Guaranteed monotonic by design
10-lead MSOP and 3 mm Г— 3 mm LFCSP_WD
2.7 V to 5.5 V power supply
Per channel power-down
Power-on reset to zero scale or midscale
Hardware LDAC and CLR functions
Serial interface; up to 50 MHz VDD VREF LDAC SCLK SYNC INPUT
REGISTER DAC
REGISTER STRING
DAC A BUFFER VOUTA INPUT
REGISTER DAC
REGISTER STRING
DAC B BUFFER VOUTB INTERFACE
LOGIC DIN AD5663
POWER-ON
RESET GND LDAC CLR APPLICATIONS POWER-DOWN
LOGIC
05855-001 Data Sheet 2.7 V to 5.5 V, 250 ОјA, Rail-to-Rail Output,
Dual 16-Bit nanoDAC
AD5663 Figure 1. Process control
Data acquisition systems …