Dual, 16-Bit, 1600 MSPS, TxDAC+
Digital-to-Analog Converter
AD9142A Data Sheet
FEATURES GENERAL DESCRIPTION Supports input data rate up to 575 MHz
Very small inherent latency variation: <2 DAC clock cycles
Proprietary low spurious and distortion design
6-carrier GSM ACLR = 79 dBc at 200 MHz IF
SFDR > 85 dBc (bandwidth = 300 MHz) at ZIF
Flexible 16-bit LVDS interface
Supports word and byte load
Data interface DLL
Sample error detection and parity
Multiple chip synchronization
Fixed latency and data generator latency compensation
Selectable 2Г—, 4Г—, 8Г— interpolation filter
Low power architecture
fS/4 power saving coarse mixer
Input signal power detection
Emergency stop for downstream analog circuitry
protection
FIFO error detection
On-chip numeric control oscillator allows carrier placement
anywhere in the DAC Nyquist bandwidth …