Datasheet Analog Devices AD9642BCPZ-250 — 数据表

FEATURES FUNCTIONAL BLOCK DIAGRAM SNR = 71.0 dBFS at 185 MHz AIN and 250 MSPS
SFDR = 83 dBc at 185 MHz AIN and 250 MSPS
−152.0 dBFS/Hz input noise at 200 MHz, −1 dBFS AIN, 250 MSPS
Total power consumption: 390 mW at 250 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Sample rates of up to 250 MSPS
Internal ADC voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
Serial port control
Energy saving power-down modes AVDD VIN+ PIPELINE
14-BIT
ADC VIN–
VCM AGND DRVDD D0±/D1± 14 PARALLEL
DDR LVDS
AND
DRIVERS AD9642 D12±/D13± DCO±
REFERENCE 1-TO-8
CLOCK
DIVIDER SERIAL PORT SCLK APPLICATIONS SDIO CSB CLK+ CLK– 09995-001 Data Sheet 14-Bit, 170 MSPS/210 MSPS/250 MSPS, …