Datasheet Analog Devices AD9648TCPZ125EPRL7 — 数据表

FEATURES FUNCTIONAL BLOCK DIAGRAM 1.8 V analog supply operation
1.8 V CMOS or LVDS outputs
SNR = 74.5 dBFS @ 70 MHz
SFDR = 91 dBc @ 70 MHz
Low power: 106 mW/channel @ 125 MSPS
Differential analog input with 650 MHz bandwidth
IF sampling frequencies to 200 MHz
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.5 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data
alignment AVDD PROGRAMMING DATA VIN+A
VIN–A VREF
SENSE
VCM AD9648 REF
SELECT MUX OPTION ADC VIN–B ADC CLK+ CLK– ORA …

14-Bit, 125 MSPS, 1.8 V Dual
Analog-to-Digital Converter
AD9648-EP Enhanced Product
FEATURES FUNCTIONAL BLOCK DIAGRAM
AVDD ADC
VIN–A VREF
SENSE RBIAS
VIN–B
ADC
VIN+B D13A
D0A
DCOA DRVDD DIVIDE
1 TO 8 DUTY CYCLE
STABILIZER MODE
CONTROLS SYNC DCS PDWN DFS OEB ORB
D13B
D0B
DCOB NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES. Figure 1. PRODUCT HIGHLIGHTS
1. APPLICATIONS
Communications
Diversity radio systems …