Datasheet Texas Instruments 74SSTUB32866AZKER — 数据表

74SSTUB32866A
www.ti.com SCAS837A – OCTOBER 2006 – REVISED NOVEMBER 2007 25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
FEATURES 1 Member of the Texas Instruments Widebus+в„ў
Family Pinout Optimizes DDR2 DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2
Registered Buffer Chip-Select Inputs Gate the Data Outputs from
Changing State and Minimizes System Power
Consumption Output Edge-Control Circuitry Minimizes
Switching Noise in an Unterminated Line
2 Supports SSTL_18 Data Inputs
Differential Clock (CLK and CLK) Inputs
Supports LVCMOS Switching Levels on the
Control and RESET Inputs
Checks Parity on DIMM-Independent Data
Inputs
Able to Cascade with a Second
74SSTUB32866A
RESET Input Disables Differential Input
Receivers, Resets All Registers, and Forces
All Outputs Low, Except QERR DESCRIPTION
This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the
1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout
configuration, two devices per DIMM are required to drive 18 SDRAM loads.
All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are …