Avoid Debugging Cycles in Power Management for FPGA,
GPU and ASIC Systems
Afshin Odabaee When it comes to designing FPGA, GPU or ASIC controlled systems, the number of
design challenges related to power management and analog systems pale in comparison
to those related to digital design. Nevertheless, it is risky to assume that power system
design can be left to “later,” or taken in line with digital design. Even seemingly innocuous
problems in power supply design can significantly delay the release of a system, as any
added time to the power system debugging cycle can halt all work on the digital side.
A good way to put DC/DC regulation
issues to rest is to use a verified development kit offered by the FPGA, GPU or
ASIC vendor. Often, the design itself or
a similar design is available as a board/
kit by the suppliers of power products
and FPGA, GPU and ASIC manufacturers. Using a tested and verified kit unburdens
system designers of most power system
and analog issues, allowing them instead
to focus their energies on configuring the
complex digital systems. The optimum
power system layout is taken care of
before significant design is undertaken. THOUGHTFUL POWER MANAGEMENT
IS CHALLENGING AT THE START Every design task is initially daunting,
and power management design is no
exception. This is the case when power is …