Datasheet Linear Technology LTC2261-14 — 数据表

制造商Linear Technology
系列LTC2261-14

14位125Msps超低功耗1.8V ADC

数据表

Datasheet LTC2261-14, LTC2260-14, LTC2259-14
PDF, 809 Kb, 语言: en, 文件上传: Aug 20, 2017, 页数: 34
14-Bit, 125Msps Ultra-Low Power 1.8V ADCs
从文件中提取

价格

打包

LTC2261CUJ-14#PBFLTC2261CUJ-14#TRPBFLTC2261IUJ-14#PBFLTC2261IUJ-14#TRPBF
N1234
Package6x6 QFN-40
包装外形图
6x6 QFN-40
包装外形图
6x6 QFN-40
包装外形图
6x6 QFN-40
包装外形图
Package CodeUJUJUJUJ
Package Index05-08-172805-08-172805-08-172805-08-1728
Pin Count40404040

参数化

Parameters / ModelsLTC2261CUJ-14#PBFLTC2261CUJ-14#TRPBFLTC2261IUJ-14#PBFLTC2261IUJ-14#TRPBF
ADC INL, LSB1111
ADCs1111
ArchitecturePipelinePipelinePipelinePipeline
Bipolar/Unipolar InputUnipolar, BipolarUnipolar, BipolarUnipolar, BipolarUnipolar, Bipolar
Bits, bits14141414
Number of Channels1111
DNL, LSB0.30.30.30.3
Demo BoardsDC1369A-A,DC1370A-A,DC1760ADC1369A-A,DC1370A-A,DC1760ADC1369A-A,DC1370A-A,DC1760ADC1369A-A,DC1370A-A,DC1760A
Design ToolsLinearLabToolsLinearLabToolsLinearLabToolsLinearLabTools
Export Controlnononono
FeaturesData Output Randomizer, Clock Duty Cycle StabilizerData Output Randomizer, Clock Duty Cycle StabilizerData Output Randomizer, Clock Duty Cycle StabilizerData Output Randomizer, Clock Duty Cycle Stabilizer
I/OParallel CMOS, Parallel DDR CMOS, Parallel DDR LVDSParallel CMOS, Parallel DDR CMOS, Parallel DDR LVDSParallel CMOS, Parallel DDR CMOS, Parallel DDR LVDSParallel CMOS, Parallel DDR CMOS, Parallel DDR LVDS
Input DriveDifferential, Single-EndedDifferential, Single-EndedDifferential, Single-EndedDifferential, Single-Ended
Input Span1Vpp to 2Vpp1Vpp to 2Vpp1Vpp to 2Vpp1Vpp to 2Vpp
Internal Referenceyesyesyesyes
Latency5555
Operating Temperature Range, °C0 to 700 to 70-40 to 85-40 to 85
Power, mW127127127127
SFDR, dB88888888
SINAD, dB73737373
SNR, dB73.473.473.473.4
Simultaneousnononono
Speed, ksps125000125000125000125000
Supply Voltage Range1.8V1.8V1.8V1.8V

生态计划

LTC2261CUJ-14#PBFLTC2261CUJ-14#TRPBFLTC2261IUJ-14#PBFLTC2261IUJ-14#TRPBF
RoHSCompliantCompliantCompliantCompliant

其他选择

LTC2259-14 LTC2259-14 LTC2260-14 LTC2260-14

设计须知

  • A Low Power, Direct-to-Digital IF Receiver with Variable Gain &mdash DN482
    PDF, 87 Kb, 档案已发布: Aug 3, 2010
    从文件中提取

文章

  • New Generation of 14-Bit 150Msps ADCs Dissipates a Third the Power of the Previous Generation without Sacrificing AC Performance &mdash LT Journal
    PDF, 545 Kb, 档案已发布: Dec 1, 2009
    从文件中提取

模型线

制造商分类

  • Data Conversion > Analog-to-Digital Converters (ADC) > High Speed ADCs (Fs >=10Msps)