Datasheet Texas Instruments TMS320TCI6484 — 数据表

制造商Texas Instruments
系列TMS320TCI6484

通信基础设施数字信号处理器

数据表

TMS320TCI6484 Communications Infrastructure Digital Signal Processor (Rev. E)
PDF, 3.0 Mb, 修订版: E, 档案已发布: Oct 30, 2009

价格

状态

TMX320TCI6484GMH
Lifecycle StatusObsolete (Manufacturer has discontinued the production of the device)
Manufacture's Sample AvailabilityNo

打包

TMX320TCI6484GMH
N1
Pin688
Package TypeGMH
Device MarkingTMX320TCI6484
Width (mm)23
Length (mm)23
Thickness (mm)2.35
Mechanical Data下载

生态计划

TMX320TCI6484GMH
RoHSNot Compliant
Pb FreeNo

应用须知

  • TI Accelerates Femtocell Deployments with DSP Solution
    PDF, 192 Kb, 档案已发布: Nov 24, 2008
  • TMS320TCI6484 Power Consumption Summary (Rev. A)
    PDF, 180 Kb, 修订版: A, 档案已发布: Mar 25, 2011
    This document discusses the power consumption of the Texas Instruments TMS320C6484 digital signal processor (DSP). The power consumption of the device is highly application-dependent. Therefore, a power spreadsheet that estimates power consumption is provided along with this application report. This spreadsheet can be used to model power consumption for user applications such as power supply desig
  • TMS320TCI6484 Memory Access Performance
    PDF, 355 Kb, 档案已发布: Jun 30, 2009
    The TMS320TCI6484 has 32KB L1D SRAM, 32KB L1P SRAM and 2MB L2 SRAM. A 32-bit 667MHz DDR2 SDRAM interface is provided on the DSP to support up to 512MB of external memory.Memory access performance is very critical for software running on the DSP. On the TCI6484 DSP, all the memories can be accessed by DSP cores and multiple DMA masters.The DSP core is capable of performing up to 128 bits
  • TMS320C6457/TMS320TCI6484/TMS320TCI6487/88 DDR2 Implementation Guidelines (Rev. D)
    PDF, 139 Kb, 修订版: D, 档案已发布: Jan 28, 2010
    This document provides implementation instructions for the DDR2 interface contained on the C6457/TCI6484/TCI6487/88 DSP.
  • TMS320TCI6484 and TMS320C6457 SERDES Implementation Guidelines (Rev. A)
    PDF, 245 Kb, 修订版: A, 档案已发布: Oct 8, 2009
    This document contains implementation instructions for the two serializer/deserializer-based interfaces (SerDes) on the TMS320TCI6484 and TMS320C6457 DSP devices:Serial RapidIOВ® (SRIO)Serial Gigabit Media Independent Interface (SGMII)
  • TMS320TCI6484 and TMS320C6457 DSPs Hardware Design Guide (Rev. B)
    PDF, 648 Kb, 修订版: B, 档案已发布: Oct 8, 2009
    This application note describes hardware system design considerations for the TMS320TCI6484 and TMS320C6457 DSPs.
  • Tuning VCP2 and TCP2 Bit Error Rate Performance
    PDF, 293 Kb, 档案已发布: Feb 11, 2011
    In most customer applications, a high level of decoding bit error rate (BER) performance is required. Since Convolutional codes and Turbo codes are widely used in wireless communication systems, TI DSPs integrate two high-performance embedded coprocessors (enhanced Viterbi decoder coprocessor and enhanced Turbo decoder coprocessor) that significantly speed up channel-decoding operations on-chip.
  • Error Detection and Correction Mechanism of TMS320C64x+/C674x (Rev. A)
    PDF, 80 Kb, 修订版: A, 档案已发布: Jul 19, 2013
    This application report describes the error detection and correction mechanism of the C64x+/C674x megamodule L1P and L2 memories implemented on some devices. Depending on the type of application, these mechanisms are used to either provide diagnostic measures to detect faults in the memory that could lead to unacceptable risk for the user or to increase the availability of the system.
  • TMS320C64x to TMS320C64x+ CPU Migration Guide (Rev. A)
    PDF, 310 Kb, 修订版: A, 档案已发布: Oct 20, 2005
    This document describes migration from the Texas Instruments TMS320C64xв„ў digital signal processor (DSP) to the TMS320C64x+в„ў DSP. The objective of this document is to indicate differences between the two cores and to briefly describe new features. Functionality in the devices that is identical is not included. For detailed information about either device, see the TMS320C64x/C64x+ DSP

模型线

系列: TMS320TCI6484 (1)

制造商分类

  • Semiconductors> Processors> Other Processors