Datasheet Texas Instruments TLV5630 — 数据表
| 制造商 | Texas Instruments |
| 系列 | TLV5630 |
2.7V至5.5V 12位8通道串行DAC，带内部基准电压源
数据表
8-Channel, 12-/10-/8-Bit, 2.7-V to 5.5-V, Low Power DAC with Power Down datasheet
PDF, 1.2 Mb, 修订版: F, 档案已发布: Nov 14, 2008
从文件中提取
状态
| TLV5630IDW | TLV5630IDWG4 | TLV5630IPW | TLV5630IPWG4 | TLV5630IPWR | TLV5630IPWRG4 | |
|---|---|---|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes | No | Yes | No | Yes | Yes |
打包
| TLV5630IDW | TLV5630IDWG4 | TLV5630IPW | TLV5630IPWG4 | TLV5630IPWR | TLV5630IPWRG4 | |
|---|---|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 | 5 | 6 |
| Pin | 20 | 20 | 20 | 20 | 20 | 20 |
| Package Type | DW | DW | PW | PW | PW | PW |
| Industry STD Term | SOIC | SOIC | TSSOP | TSSOP | TSSOP | TSSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G |
| Package QTY | 25 | 25 | 70 | 70 | 2000 | 2000 |
| Carrier | TUBE | TUBE | TUBE | TUBE | LARGE T&R | LARGE T&R |
| Device Marking | TLV5630I | TLV5630I | TY5630 | TY5630 | TY5630 | TY5630 |
| Width (mm) | 7.5 | 7.5 | 4.4 | 4.4 | 4.4 | 4.4 |
| Length (mm) | 12.8 | 12.8 | 6.5 | 6.5 | 6.5 | 6.5 |
| Thickness (mm) | 2.35 | 2.35 | 1 | 1 | 1 | 1 |
| Pitch (mm) | 1.27 | 1.27 | .65 | .65 | .65 | .65 |
| Max Height (mm) | 2.65 | 2.65 | 1.2 | 1.2 | 1.2 | 1.2 |
| Mechanical Data | 下载 | 下载 | 下载 | 下载 | 下载 | 下载 |
参数化
| Parameters / Models | TLV5630IDW | TLV5630IDWG4 | TLV5630IPW | TLV5630IPWG4 | TLV5630IPWR | TLV5630IPWRG4 |
|---|---|---|---|---|---|---|
| Code to Code Glitch(Typ), nV-sec | 4 | 4 | 4 | 4 | 4 | 4 |
| DAC Architecture | String | String | String | String | String | String |
| DAC Channels | 8 | 8 | 8 | 8 | 8 | 8 |
| Gain Error(Max), %FSR | 0.6 | 0.6 | 0.6 | 0.6 | 0.6 | 0.6 |
| INL(Max), +/-LSB | 6 | 6 | 6 | 6 | 6 | 6 |
| Interface | SPI | SPI | SPI | SPI | SPI | SPI |
| Offset Error(Max), % | N/A | N/A | N/A | N/A | N/A | N/A |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 |
| Output Range Max., mA/V | 5.1 | 5.1 | 5.1 | 5.1 | 5.1 | 5.1 |
| Output Type | Buffered Voltage | Buffered Voltage | Buffered Voltage | Buffered Voltage | Buffered Voltage | Buffered Voltage |
| Package Group | SOIC | SOIC | TSSOP | TSSOP | TSSOP | TSSOP |
| Package Size: mm2:W x L, PKG | 20SOIC: 132 mm2: 10.3 x 12.8(SOIC) | 20SOIC: 132 mm2: 10.3 x 12.8(SOIC) | 20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP) | 20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP) | 20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP) | 20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP) |
| Power Consumption(Typ), mW | 18 | 18 | 18 | 18 | 18 | 18 |
| Rating | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog |
| Reference: Type | Ext,Int | Ext,Int | Ext,Int | Ext,Int | Ext,Int | Ext,Int |
| Resolution, Bits | 12 | 12 | 12 | 12 | 12 | 12 |
| Sample / Update Rate, MSPS | 0.283 | 0.283 | 0.283 | 0.283 | 0.283 | 0.283 |
| Settling Time, µs | 1 | 1 | 1 | 1 | 1 | 1 |
| Special Features | SDO | SDO | SDO | SDO | SDO | SDO |
| Zero Code Error(Typ), mV | 30 | 30 | 30 | 30 | 30 | 30 |
生态计划
| TLV5630IDW | TLV5630IDWG4 | TLV5630IPW | TLV5630IPWG4 | TLV5630IPWR | TLV5630IPWRG4 | |
|---|---|---|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant |
模型线
系列: TLV5630 (6)
制造商分类
- Semiconductors> Data Converters> Digital-to-Analog Converters (DACs)> Precision DACs (=<10MSPS)