Datasheet Texas Instruments TLC5510 — 数据表

制造商Texas Instruments
系列TLC5510
Datasheet Texas Instruments TLC5510

8位20MSPS模数转换器(ADC)

数据表

8-Bit High-Speed Analog-to-Digital Converters datasheet
PDF, 892 Kb, 修订版: L, 档案已发布: Jun 11, 2003
从文件中提取

价格

状态

TLC5510INSTLC5510INSLETLC5510INSRTLC5510IPWTLC5510IPWR
Lifecycle StatusActive (Recommended for new designs)Obsolete (Manufacturer has discontinued the production of the device)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesNoNoYesNo

打包

TLC5510INSTLC5510INSLETLC5510INSRTLC5510IPWTLC5510IPWR
N12345
Pin2424242424
Package TypeNSNSNSPWPW
Industry STD TermSOPSOPSOPTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY342000602000
CarrierTUBELARGE T&RTUBELARGE T&R
Device MarkingTLC5510ITLC5510IY5510Y5510
Width (mm)5.35.35.34.44.4
Length (mm)1515157.87.8
Thickness (mm)1.951.951.9511
Pitch (mm)1.271.271.27.65.65
Max Height (mm)2221.21.2
Mechanical Data下载下载下载下载下载

参数化

Parameters / ModelsTLC5510INS
TLC5510INS
TLC5510INSLE
TLC5510INSLE
TLC5510INSR
TLC5510INSR
TLC5510IPW
TLC5510IPW
TLC5510IPWR
TLC5510IPWR
# Input Channels11111
Analog Input BW, MHz14141414
Analog Input BW(MHz)14
Approx. Price (US$)2.59 | 1ku
ArchitectureFlashFlashFlashFlashFlash
DNL(Max), +/-LSB0.750.750.750.75
DNL(Max)(+/-LSB)0.75
DNL(Typ), +/-LSB0.30.30.30.3
ENOB, Bits6.86.86.86.8
INL(Max), +/-LSB1111
INL(Max)(+/-LSB)1
INL(Typ), +/-LSB0.40.40.40.4
Input BufferNoNoNoNoNo
Input Range, Vp-p2+2V222
InterfaceParallel CMOSParallel CMOSParallel CMOSParallel CMOSParallel CMOS
Operating Temperature Range, C-20 to 75-20 to 75-20 to 75-20 to 75
Operating Temperature Range(C)-20 to 75
Package GroupSOSOSOTSSOPTSSOP
Package Size: mm2:W x L, PKG24SO: 117 mm2: 7.8 x 15(SO)24SO: 117 mm2: 7.8 x 15(SO)24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)
Package Size: mm2:W x L (PKG)24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)
Power Consumption(Typ), mW127.5127.5127.5127.5
Power Consumption(Typ)(mW)127.5
RatingCatalogCatalogCatalogCatalogCatalog
Reference ModeExtExtExtExtExt
Resolution, Bits8888
Resolution(Bits)8
SFDR, dB42424242
SFDR(dB)42
SINAD, dB44444444
SNR, dB46464646
SNR(dB)46
Sample Rate(Max), MSPS20202020
Sample Rate(Max)(MSPS)20

生态计划

TLC5510INSTLC5510INSLETLC5510INSRTLC5510IPWTLC5510IPWR
RoHSCompliantNot CompliantCompliantCompliantCompliant
Pb FreeNo

应用须知

  • Interfacing the TLC5510 Analog-to-Digital Converter to the TMS320C203 DSP
    PDF, 401 Kb, 档案已发布: Apr 27, 2000
    This application report is a summary of the application note titled Interfacing the TLC5510 Analog-to-Digital Converter to the TMS320C203 DSP (literature number SLAA029) that presents guidelines for interfacing the TI TLC5510 analog-to-digital converter (ADC) to the TI TMS320C203 DSP. The TLC5510 is a CMOS, 8-bit, 20 MSPS (megasamples per second) ADC utilizing a semi-flash architecture. The TLC551
  • Interfacing A/D Converters TLC5540/10 to the DSKplus DSP Starter Kit TMS320C54x
    PDF, 206 Kb, 档案已发布: Apr 1, 1997
    This Application Note describes the construction of a test circuit using the A/D converters TLC5540 and TLC5510, and alternative ways of interfacing these converters to the DSKplus DSP starter kit TMS320C54x. Details are given of the test circuit of the TLC5540/10 and of the interface, and the programming of the digital signal processor TMS320C54x is also described.
  • Interfacing the TLC5510 Analog-to-Digital Converter to the TMS320C203 DSP
    PDF, 540 Kb, 档案已发布: Feb 1, 1998
    This application report presents guidelines for interfacing the Texas Instruments (TI(TM)) TLC5510 8-bit parallel-output analog-to-digital converter (ADC) to the TI TMS320C203 DSP data bus. The 8-bit ADC operates at a rate of 20 MHz. The C callable application program (assembly code) used to initialize the TMS320C203 and execute the code is also discussed.This report serves as reference inform
  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, 档案已发布: Sep 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, 档案已发布: Apr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, 修订版: A, 档案已发布: Sep 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, 档案已发布: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers

模型线

制造商分类

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)