Datasheet Texas Instruments SN74LVTH540 — 数据表

制造商	Texas Instruments
系列	SN74LVTH540

具有三态输出的3.3V ABT八路缓冲器/驱动器

数据表

PDF, 876 Kb, 修订版: G, 档案已发布: Oct 10, 2003

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	SN74LVTH540DBLE	SN74LVTH540DBR	SN74LVTH540DW	SN74LVTH540DWR	SN74LVTH540PW	SN74LVTH540PWG4	SN74LVTH540PWLE	SN74LVTH540PWR
Lifecycle Status	Obsolete (Manufacturer has discontinued the production of the device)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Active (Recommended for new designs)	Obsolete (Manufacturer has discontinued the production of the device)	Active (Recommended for new designs)
Manufacture's Sample Availability	No	No	No	No	No	No	Yes	No

	SN74LVTH540DBLE	SN74LVTH540DBR	SN74LVTH540DW	SN74LVTH540DWR	SN74LVTH540PW	SN74LVTH540PWG4	SN74LVTH540PWLE	SN74LVTH540PWR
N	1	2	3	4	5	6	7	8
Pin	20	20	20	20	20	20	20	20
Package Type	DB	DB	DW	DW	PW	PW	PW	PW
Industry STD Term	SSOP	SSOP	SOIC	SOIC	TSSOP	TSSOP	TSSOP	TSSOP
JEDEC Code	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G	R-PDSO-G
Width (mm)	5.3	5.3	7.5	7.5	4.4	4.4	4.4	4.4
Length (mm)	7.2	7.2	12.8	12.8	6.5	6.5	6.5	6.5
Thickness (mm)	1.95	1.95	2.35	2.35	1	1	1	1
Pitch (mm)	.65	.65	1.27	1.27	.65	.65	.65	.65
Max Height (mm)	2	2	2.65	2.65	1.2	1.2	1.2	1.2
Mechanical Data	下载	下载	下载	下载	下载	下载	下载	下载
Package QTY		2000	25	2000	70	70		2000
Carrier		LARGE T&R	TUBE	LARGE T&R	TUBE	TUBE		LARGE T&R
Device Marking		LXH540	LVTH540	LVTH540	LXH540	LXH540		LXH540

Parameters / Models	SN74LVTH540DBLE	SN74LVTH540DBR	SN74LVTH540DW	SN74LVTH540DWR	SN74LVTH540PW	SN74LVTH540PWG4	SN74LVTH540PWLE	SN74LVTH540PWR
Approx. Price (US$)	0.55 \| 1ku						0.55 \| 1ku
Bits		8	8	8	8	8		8
Bits(#)	8						8
F @ Nom Voltage(Max), Mhz		160	160	160	160	160		160
F @ Nom Voltage(Max)(Mhz)	160						160
ICC @ Nom Voltage(Max), mA		0.005	0.005	0.005	0.005	0.005		0.005
ICC @ Nom Voltage(Max)(mA)	0.005						0.005
Input Type	CMOS TTL						CMOS TTL
Operating Temperature Range, C		-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85		-40 to 85
Operating Temperature Range(C)	-40 to 85						-40 to 85
Output Drive (IOL/IOH)(Max), mA		-32/64	-32/64	-32/64	-32/64	-32/64		-32/64
Output Drive (IOL/IOH)(Max)(mA)	-32/64						-32/64
Output Type	CMOS						CMOS
Package Group	SSOP	SSOP	SOIC	SOIC	TSSOP	TSSOP	TSSOP	TSSOP
Package Size: mm2:W x L, PKG		20SSOP: 56 mm2: 7.8 x 7.2(SSOP)	20SOIC: 132 mm2: 10.3 x 12.8(SOIC)	20SOIC: 132 mm2: 10.3 x 12.8(SOIC)	20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)	20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)		20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)
Package Size: mm2:W x L (PKG)	20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)						20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
Schmitt Trigger	No	No	No	No	No	No	No	No
Technology Family	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT
VCC(Max), V		3.6	3.6	3.6	3.6	3.6		3.6
VCC(Max)(V)	3.6						3.6
VCC(Min), V		2.7	2.7	2.7	2.7	2.7		2.7
VCC(Min)(V)	2.7						2.7
Voltage(Nom), V		3.3	3.3	3.3	3.3	3.3		3.3
Voltage(Nom)(V)	3.3						3.3
tpd @ Nom Voltage(Max), ns		4.6	4.6	4.6	4.6	4.6		4.6
tpd @ Nom Voltage(Max)(ns)	4.6						4.6

	SN74LVTH540DBLE	SN74LVTH540DBR	SN74LVTH540DW	SN74LVTH540DWR	SN74LVTH540PW	SN74LVTH540PWG4	SN74LVTH540PWLE	SN74LVTH540PWR
RoHS	Not Compliant	Compliant	Compliant	Compliant	Compliant	Compliant	Not Compliant	Compliant
Pb Free	No	No

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LVT Family Characteristics (Rev. A)
PDF, 98 Kb, 修订版: A, 档案已发布: Mar 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
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LVT-to-LVTH Conversion
PDF, 84 Kb, 档案已发布: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
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Bus-Hold Circuit
PDF, 418 Kb, 档案已发布: Feb 5, 2001
When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

系列: SN74LVTH540 (8)