Datasheet Texas Instruments SN74LVTH16244A-EP — 数据表

制造商Texas Instruments
系列SN74LVTH16244A-EP
Datasheet Texas Instruments SN74LVTH16244A-EP

具有三态输出的增强型产品3.3V Abt 16位缓冲器/驱动器

数据表

SN74LVTH16244A-EP datasheet
PDF, 707 Kb, 修订版: F, 档案已发布: Apr 23, 2007
从文件中提取

价格

状态

8W244AMDGGREPG4CLVTH16244AIDGVREPCLVTH16244AMDGGREPCLVTH16244AQDGGREPCLVTH16244AQDLREPV62/04601-01XEV62/04601-01YEV62/04601-02UAV62/04601-02ZEV62/04601-03YE
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNoNoNoNoNo

打包

8W244AMDGGREPG4CLVTH16244AIDGVREPCLVTH16244AMDGGREPCLVTH16244AQDGGREPCLVTH16244AQDLREPV62/04601-01XEV62/04601-01YEV62/04601-02UAV62/04601-02ZEV62/04601-03YE
N12345678910
Pin48484848484848564848
Package TypeDGGDGVDGGDGGDLDLDGGZQLDGVDGG
Industry STD TermTSSOPTVSOPTSSOPTSSOPSSOPSSOPTSSOPBGA MICROSTAR JUNIORTVSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PBGA-NR-PDSO-GR-PDSO-G
Package QTY200020002000200010001000200020002000
CarrierLARGE T&RLARGE T&RLARGE T&RLARGE T&RLARGE T&RLARGE T&RLARGE T&RLARGE T&RLARGE T&R
Device MarkingH16244AMEPLL244AEPH16244AMEPLH16244AEPLH16244AEPLH16244AEPLH16244AEPLL244AEPLL244AEPH16244AMEP
Width (mm)6.14.46.16.17.497.496.14.54.46.1
Length (mm)12.59.712.512.515.8815.8812.579.712.5
Thickness (mm)1.151.051.151.152.592.591.15.751.051.15
Pitch (mm).5.4.5.5.635.635.5.65.4.5
Max Height (mm)1.21.21.21.22.792.791.211.21.2
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参数化

Parameters / Models8W244AMDGGREPG4
8W244AMDGGREPG4
CLVTH16244AIDGVREP
CLVTH16244AIDGVREP
CLVTH16244AMDGGREP
CLVTH16244AMDGGREP
CLVTH16244AQDGGREP
CLVTH16244AQDGGREP
CLVTH16244AQDLREP
CLVTH16244AQDLREP
V62/04601-01XE
V62/04601-01XE
V62/04601-01YE
V62/04601-01YE
V62/04601-02UA
V62/04601-02UA
V62/04601-02ZE
V62/04601-02ZE
V62/04601-03YE
V62/04601-03YE
Bits161616161616161616
Bits(#)16
Input TypeTTL/CMOSTTL/CMOSTTL/CMOSTTL/CMOSTTL/CMOSTTL/CMOSTTL/CMOSTTL/CMOSTTL/CMOSTTL/CMOS
Operating Temperature Range, C-40 to 125,-40 to 85,-55 to 125-40 to 125,-40 to 85,-55 to 125-40 to 125,-40 to 85,-55 to 125-40 to 125,-40 to 85,-55 to 125-40 to 125,-40 to 85,-55 to 125-40 to 125,-40 to 85,-55 to 125-40 to 125,-40 to 85,-55 to 125-40 to 125,-40 to 85,-55 to 125-40 to 125,-40 to 85,-55 to 125
Operating Temperature Range(C)-40 to 125
-40 to 85
-55 to 125
Output TypeLVTTLLVTTLLVTTLLVTTLLVTTLLVTTLLVTTLLVTTLLVTTLLVTTL
Package GroupTSSOPTVSOPTSSOPTSSOPSSOPSSOPTSSOPBGA MICROSTAR JUNIORTVSOPTSSOP
Package Size: mm2:W x L, PKG48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)48TVSOP: 62 mm2: 6.4 x 9.7(TVSOP)48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)48SSOP: 164 mm2: 10.35 x 15.88(SSOP)48SSOP: 164 mm2: 10.35 x 15.88(SSOP)48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)48TVSOP: 62 mm2: 6.4 x 9.7(TVSOP)48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)
Package Size: mm2:W x L (PKG)56BGA MICROSTAR JUNIOR: 32 mm2: 4.5 x 7(BGA MICROSTAR JUNIOR)
RatingHiRel Enhanced ProductHiRel Enhanced ProductHiRel Enhanced ProductHiRel Enhanced ProductHiRel Enhanced ProductHiRel Enhanced ProductHiRel Enhanced ProductHiRel Enhanced ProductHiRel Enhanced ProductHiRel Enhanced Product
Schmitt TriggerNoNoNoNoNoNoNoNoNoNo
Technology FamilyLVTLVTLVTLVTLVTLVTLVTLVTLVTLVT
VCC(Max), V3.63.63.63.63.63.63.63.63.6
VCC(Max)(V)3.6
VCC(Min), V2.72.72.72.72.72.72.72.72.7
VCC(Min)(V)2.7
Voltage(Nom), V3.33.33.33.33.33.33.33.33.3
Voltage(Nom)(V)3.3

生态计划

8W244AMDGGREPG4CLVTH16244AIDGVREPCLVTH16244AMDGGREPCLVTH16244AQDGGREPCLVTH16244AQDLREPV62/04601-01XEV62/04601-01YEV62/04601-02UAV62/04601-02ZEV62/04601-03YE
RoHSCompliantCompliantCompliantCompliantCompliantCompliantCompliantNot CompliantCompliantCompliant
Pb FreeNo

应用须知

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, 修订版: A, 档案已发布: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, 档案已发布: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, 修订版: B, 档案已发布: May 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
    PDF, 105 Kb, 修订版: A, 档案已发布: Aug 1, 1997
    The spectrum of bus-interface devices with damping resistors or balanced/light output drive currently offered by various logic vendors is confusing at best. Inconsistencies in naming conventions and methods used for implementation make it difficult to identify the best solution for a given application. This report attempts to clarify the issue by looking at several vendors? approaches and discussi
  • Understanding Advanced Bus-Interface Products Design Guide
    PDF, 253 Kb, 档案已发布: May 1, 1996
  • Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
    PDF, 209 Kb, 档案已发布: May 10, 2002
    Many telecom and networking applications require that cards be inserted and extracted from a live backplane without interrupting data or damaging components. To achieve this interface terminals of the card must be electrically isolated from the bus system during insertion or extraction from the backplane. To facilitate this Texas Instruments provides bus-interface and logic devices with features

模型线

制造商分类

  • Semiconductors> Space & High Reliability> Logic Products> Buffers/Drivers/Transceivers> Buffer Drivers