Datasheet Texas Instruments SN74LVT8996PW — 数据表

制造商Texas Instruments
系列SN74LVT8996
零件号SN74LVT8996PW
Datasheet Texas Instruments SN74LVT8996PW

3.3V ABT 10位可寻址扫描端口多点可寻址IEEE STD 1149.1(JTAG)TAP收发器24-TSSOP -40至85

数据表

3.3-V 10-Bit Addressable Scan Ports Multidrop-Addressable IEEE Std 1149.1 (JTAG) datasheet
PDF, 1.3 Mb, 修订版: A, 档案已发布: Dec 2, 1999
从文件中提取

价格

状态

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

打包

Pin24
Package TypePW
Industry STD TermTSSOP
JEDEC CodeR-PDSO-G
Package QTY60
CarrierTUBE
Device MarkingLX8996
Width (mm)4.4
Length (mm)7.8
Thickness (mm)1
Pitch (mm).65
Max Height (mm)1.2
Mechanical Data下载

参数化

Bits10
ICC @ Nom Voltage(Max)20 mA
Operating Temperature Range-40 to 85 C
Output Drive (IOL/IOH)(Max)64/-32 mA
Package GroupTSSOP
Package Size: mm2:W x L24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP) PKG
RatingCatalog
Technology FamilyLVT
VCC(Max)3.6 V
VCC(Min)2.7 V

生态计划

RoHSCompliant

应用须知

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, 修订版: A, 档案已发布: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, 档案已发布: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.

模型线

制造商分类

  • Semiconductors > Logic > Specialty Logic > Boundary Scan (JTAG) Logic