Datasheet Texas Instruments SN74LVT8986PM — 数据表

制造商Texas Instruments
系列SN74LVT8986
零件号SN74LVT8986PM
Datasheet Texas Instruments SN74LVT8986PM

3.3V 链接可寻址扫描端口多点可寻址 IEEE STD 1149.1 (JTAG) Tap 收发器 64-LQFP -40 至 85

数据表

3.3-V Linking Addressable Scan Ports Multidrop-Addressable IEEE STD 1149.1 (JTAG datasheet
PDF, 905 Kb, 修订版: E, 档案已发布: May 14, 2007
从文件中提取

价格

状态

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityYes

打包

Pin64
Package TypePM
Industry STD TermLQFP
JEDEC CodeS-PQFP-G
Package QTY160
CarrierJEDEC TRAY (10+1)
Device MarkingLVT8986
Width (mm)10
Length (mm)10
Thickness (mm)1.4
Pitch (mm).5
Max Height (mm)1.6
Mechanical Data下载

生态计划

RoHSCompliant

应用须知

  • Cascading Multiple Linking Addressable Scan Port Devices
    PDF, 216 Kb, 档案已发布: Nov 5, 2002
    This application report is intended to illustrate the capability of cascading multiple Texas Instruments (TI) linking addressable scan port (LASP) devices. It explains configuring the secondary test access ports (TAPs) of cascaded LASPs with the help of a single linking shadow protocol and protocol-bypass inputs. Several examples of linking shadow protocol, along with timing requirements and scan
  • Programming CPLDs Via the 'LVT8986 LASP
    PDF, 819 Kb, 档案已发布: Nov 1, 2005
    This application report summarizes key information required for understanding the 'LVT8986 linking addressable scan ports (LASPs) multidrop addressable IEEE Std 1149.1 (JTAG) test access port (TAP) transceiver. This report includes information about the 'LVT8986 secondary TAPs, bypass and linking shadow protocol, scan-path description languages, serial vector format files, and an example of how to
  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, 修订版: A, 档案已发布: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, 档案已发布: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.

模型线

系列: SN74LVT8986 (2)

制造商分类

  • Semiconductors > Logic > Specialty Logic > Boundary Scan (JTAG) Logic