Datasheet Texas Instruments SN74LVT16240 — 数据表

制造商Texas Instruments
系列SN74LVT16240
Datasheet Texas Instruments SN74LVT16240

具有三态输出的3.3V ABT 16位缓冲器/驱动器

数据表

SN54LVT16240, SN74LVT16240 datasheet
PDF, 316 Kb, 修订版: A, 档案已发布: Nov 1, 2006
从文件中提取

价格

状态

SN74LVT16240DGGRSN74LVT16240DLSN74LVT16240DLR
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNo

打包

SN74LVT16240DGGRSN74LVT16240DLSN74LVT16240DLR
N123
Pin484848
Package TypeDGGDLDL
Industry STD TermTSSOPSSOPSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY2000251000
CarrierLARGE T&RTUBELARGE T&R
Device MarkingLVT16240LVT16240LVT16240
Width (mm)6.17.497.49
Length (mm)12.515.8815.88
Thickness (mm)1.152.592.59
Pitch (mm).5.635.635
Max Height (mm)1.22.792.79
Mechanical Data下载下载下载

参数化

Parameters / ModelsSN74LVT16240DGGR
SN74LVT16240DGGR
SN74LVT16240DL
SN74LVT16240DL
SN74LVT16240DLR
SN74LVT16240DLR
Bits161616
F @ Nom Voltage(Max), Mhz160160160
ICC @ Nom Voltage(Max), mA0.0050.0050.005
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA-32/64-32/64-32/64
Package GroupTSSOPSSOPSSOP
Package Size: mm2:W x L, PKG48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP)48SSOP: 164 mm2: 10.35 x 15.88(SSOP)48SSOP: 164 mm2: 10.35 x 15.88(SSOP)
RatingCatalogCatalogCatalog
Schmitt TriggerNoNoNo
Technology FamilyLVTLVTLVT
VCC(Max), V3.63.63.6
VCC(Min), V2.72.72.7
Voltage(Nom), V3.33.33.3
tpd @ Nom Voltage(Max), ns444

生态计划

SN74LVT16240DGGRSN74LVT16240DLSN74LVT16240DLR
RoHSCompliantCompliantCompliant

应用须知

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, 修订版: A, 档案已发布: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, 档案已发布: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.

模型线

制造商分类

  • Semiconductors> Logic> Buffer/Driver/Transceiver> Inverting Buffer/Driver