Datasheet Texas Instruments SN74LVT125-EP — 数据表
| 制造商 | Texas Instruments |
| 系列 | SN74LVT125-EP |
具有三态输出的增强型产品3.3V Abt四路总线缓冲器
数据表
价格
状态
| SN74LVT125QPWREP | V62/04705-01XE | |
|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | No |
打包
| SN74LVT125QPWREP | V62/04705-01XE | |
|---|---|---|
| N | 1 | 2 |
| Pin | 14 | 14 |
| Package Type | PW | PW |
| Industry STD Term | TSSOP | TSSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G |
| Package QTY | 2000 | 2000 |
| Carrier | LARGE T&R | LARGE T&R |
| Device Marking | LVT125E | LVT125E |
| Width (mm) | 4.4 | 4.4 |
| Length (mm) | 5 | 5 |
| Thickness (mm) | 1 | 1 |
| Pitch (mm) | .65 | .65 |
| Max Height (mm) | 1.2 | 1.2 |
| Mechanical Data | 下载 | 下载 |
参数化
| Parameters / Models | SN74LVT125QPWREP | V62/04705-01XE |
|---|---|---|
| Bits | 4 | 4 |
| Input Type | TTL/CMOS | TTL/CMOS |
| Operating Temperature Range, C | -40 to 125 | -40 to 125 |
| Output Type | LVTTL | LVTTL |
| Package Group | TSSOP | TSSOP |
| Package Size: mm2:W x L, PKG | 14TSSOP: 32 mm2: 6.4 x 5(TSSOP) | 14TSSOP: 32 mm2: 6.4 x 5(TSSOP) |
| Rating | HiRel Enhanced Product | HiRel Enhanced Product |
| Schmitt Trigger | No | No |
| Technology Family | LVT | LVT |
| VCC(Max), V | 3.6 | 3.6 |
| VCC(Min), V | 2.7 | 2.7 |
| Voltage(Nom), V | 3.3 | 3.3 |
生态计划
| SN74LVT125QPWREP | V62/04705-01XE | |
|---|---|---|
| RoHS | Compliant | Compliant |
应用须知
- LVT Family Characteristics (Rev. A)PDF, 98 Kb, 修订版: A, 档案已发布: Mar 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti - LVT-to-LVTH ConversionPDF, 84 Kb, 档案已发布: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
模型线
系列: SN74LVT125-EP (2)
制造商分类
- Semiconductors> Space & High Reliability> Logic Products> Buffers/Drivers/Transceivers> Buffer Drivers