Datasheet Texas Instruments 74AVC16373DGGRG4 — 数据表

制造商Texas Instruments
系列SN74AVC16373
零件号74AVC16373DGGRG4
Datasheet Texas Instruments 74AVC16373DGGRG4

具有三态输出的16位透明D类锁存器48-TSSOP -40至85

数据表

16-Bit Transparent D-Type Latch With 3-State Outputs datasheet
PDF, 873 Kb, 修订版: H, 档案已发布: Sep 12, 2008
从文件中提取

价格

状态

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityYes

打包

Pin48
Package TypeDGG
Industry STD TermTSSOP
JEDEC CodeR-PDSO-G
Package QTY2000
CarrierLARGE T&R
Device MarkingAVC16373
Width (mm)6.1
Length (mm)12.5
Thickness (mm)1.15
Pitch (mm).5
Max Height (mm)1.2
Mechanical Data下载

参数化

3-State OutputYes
Bits16
F @ Nom Voltage(Max)200 Mhz
ICC @ Nom Voltage(Max)0.04 mA
Operating Temperature Range-40 to 85 C
Output Drive (IOL/IOH)(Max)12/-12 mA
Package GroupTSSOP
Package Size: mm2:W x L48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP) PKG
RatingCatalog
Schmitt TriggerNo
Technology FamilyAVC
VCC(Max)3.6 V
VCC(Min)1.4 V
Voltage(Nom)1.2,1.5,1.8,2.5,3.3 V
tpd @ Nom Voltage(Max)5.8,6.8,5.7,3.3,2.8 ns

生态计划

RoHSCompliant

应用须知

  • Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B)
    PDF, 126 Kb, 修订版: B, 档案已发布: Jul 7, 1999
    Texas Instruments (TI[TM]) next-generation logic is called the Advanced Very-low-voltage CMOS (AVC) family. The AVCfamily features TI?s Dynamic Output Control (DOC[TM]) circuit (patent pending). DOC circuitry automatically lowers the outputimpedance of the circuit at the beginning of a signal transition, providing enough current to achieve high signaling speeds, thensubsequently raises the i
  • AVC Logic Family Technology and Applications (Rev. A)
    PDF, 148 Kb, 修订版: A, 档案已发布: Aug 26, 1998
    Texas Instruments (TI?) announces the industry?s first logic family to achieve maximum propagation delays of less than 2 ns at 2.5 V. TI?s next-generation logic is the Advanced Very-low-voltage CMOS (AVC) family. Although optimized for 2.5-V systems, AVC logic supports mixed-voltage systems because it is compatible with 3.3-V and 1.8-V devices. The AVC family features TI?s Dynamic Output Control (
  • Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B)
    PDF, 390 Kb, 修订版: B, 档案已发布: Apr 30, 2015
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, 修订版: B, 档案已发布: May 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Selecting the Right Level Translation Solution (Rev. A)
    PDF, 313 Kb, 修订版: A, 档案已发布: Jun 22, 2004
    Supply voltages continue to migrate to lower nodes to support today's low-power high-performance applications. While some devices are capable of running at lower supply nodes others might not have this capability. To haveswitching compatibility between these devices the output of each driver must be compliant with the input of the receiver that it is driving. There are several level-translati
  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Kb, 修订版: A, 档案已发布: Feb 6, 2015

模型线

制造商分类

  • Semiconductors > Logic > Flip-Flop/Latch/Register > D-Type Latch