Datasheet Texas Instruments SN74ALVCH16821 — 数据表

制造商Texas Instruments
系列SN74ALVCH16821
Datasheet Texas Instruments SN74ALVCH16821

具有三态输出的3.3V 20位总线接口触发器

数据表

SN74ALVCH16821 datasheet
PDF, 313 Kb, 修订版: F, 档案已发布: Aug 30, 2004
从文件中提取

价格

状态

SN74ALVCH16821DGGRSN74ALVCH16821DL
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNo

打包

SN74ALVCH16821DGGRSN74ALVCH16821DL
N12
Pin5656
Package TypeDGGDL
Industry STD TermTSSOPSSOP
JEDEC CodeR-PDSO-GR-PDSO-G
Package QTY200020
CarrierLARGE T&RTUBE
Device MarkingALVCH16821ALVCH16821
Width (mm)6.17.49
Length (mm)1418.41
Thickness (mm)1.152.59
Pitch (mm).5.635
Max Height (mm)1.22.79
Mechanical Data下载下载

参数化

Parameters / ModelsSN74ALVCH16821DGGR
SN74ALVCH16821DGGR
SN74ALVCH16821DL
SN74ALVCH16821DL
3-State OutputYesYes
Bits2020
F @ Nom Voltage(Max), Mhz150150
ICC @ Nom Voltage(Max), mA0.040.04
Operating Temperature Range, C-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA24/-2424/-24
Package GroupTSSOPSSOP
Package Size: mm2:W x L, PKG56TSSOP: 113 mm2: 8.1 x 14(TSSOP)56SSOP: 191 mm2: 10.35 x 18.42(SSOP)
RatingCatalogCatalog
Schmitt TriggerNoNo
Technology FamilyALVCALVC
VCC(Max), V3.63.6
VCC(Min), V1.651.65
Voltage(Nom), V1.8,2.5,2.7,3.31.8,2.5,2.7,3.3
tpd @ Nom Voltage(Max), ns5.8,5.3,4.55.8,5.3,4.5

生态计划

SN74ALVCH16821DGGRSN74ALVCH16821DL
RoHSCompliantCompliant

应用须知

  • TI SN74ALVC16835 Component Specification Analysis for PC100
    PDF, 43 Kb, 档案已发布: Aug 3, 1998
    The PC100 standard establishes design parameters for the PC SDRAM DIMM that is designed to operate at 100 MHz. The 168-pin, 8-byte, registered SDRAM DIMM is a JEDEC-defined device (JC-42.5-96-146A). Some of the defined signal paths include data signals, address signals, and control signals. This application report discusses the SN74ALVC16835 18-bit universal bus driver that is available from T
  • Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)
    PDF, 96 Kb, 修订版: A, 档案已发布: May 13, 1998
    Design of high-performance personal computer (PC) systems that are capable of meeting the needs imposed by modern operating systems and software includes the use of large banks of SDRAMs on DIMMs (see Figure 1).To meet the demands of stable functionality over the broad spectrum of operating environments, meet system timing needs, and to support data integrity, the loads presented by the large
  • Bus-Hold Circuit
    PDF, 418 Kb, 档案已发布: Feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, 修订版: B, 档案已发布: May 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)
    PDF, 154 Kb, 修订版: A, 档案已发布: Sep 8, 1999
    In the last few years the trend toward reducing supply voltage (VCC) has continued as reflected in an additional specification of 2.5-V VCC for the AVC ALVT ALVC LVC LV and the CBTLV families.In this application report the different logic levels at VCC of 5 V 3.3 V 2.5 V and 1.8 V are compared. Within the report the possibilities for migration from 5-V logic and 3.3-V logic families

模型线

系列: SN74ALVCH16821 (2)

制造商分类

  • Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Flip-Flop