Datasheet Texas Instruments SN74ALVC08 — 数据表

制造商Texas Instruments
系列SN74ALVC08
Datasheet Texas Instruments SN74ALVC08

四路2输入正与门

数据表

SN74ALVC08 datasheet
PDF, 778 Kb, 修订版: I, 档案已发布: Aug 31, 2004
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价格

状态

SN74ALVC08DSN74ALVC08DG4SN74ALVC08DGVRSN74ALVC08DRSN74ALVC08DRE4SN74ALVC08DRG4SN74ALVC08NSRSN74ALVC08PWRSN74ALVC08PWRE4SN74ALVC08PWRG4SN74ALVC08RGYRSN74ALVC08RGYRG4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoYesNoYesNoNoNoNoNoNo

打包

SN74ALVC08DSN74ALVC08DG4SN74ALVC08DGVRSN74ALVC08DRSN74ALVC08DRE4SN74ALVC08DRG4SN74ALVC08NSRSN74ALVC08PWRSN74ALVC08PWRE4SN74ALVC08PWRG4SN74ALVC08RGYRSN74ALVC08RGYRG4
N123456789101112
Pin141414141414141414141414
Package TypeDDDGVDDDNSPWPWPWRGYRGY
Industry STD TermSOICSOICTVSOPSOICSOICSOICSOPTSSOPTSSOPTSSOPVQFNVQFN
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GS-PQFP-NS-PQFP-N
Package QTY50502000250025002500200020002000200030003000
CarrierTUBETUBELARGE T&RLARGE T&RLARGE T&RLARGE T&RLARGE T&RLARGE T&RLARGE T&RLARGE T&RLARGE T&RLARGE T&R
Device MarkingALVC08ALVC08VA08ALVC08ALVC08ALVC08ALVC08VA08VA08VA08VA08VA08
Width (mm)3.913.914.43.913.913.915.34.44.44.43.53.5
Length (mm)8.658.653.68.658.658.6510.35553.53.5
Thickness (mm)1.581.581.051.581.581.581.95111.9.9
Pitch (mm)1.271.27.41.271.271.271.27.65.65.65.5.5
Max Height (mm)1.751.751.21.751.751.7521.21.21.211
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参数化

Parameters / ModelsSN74ALVC08D
SN74ALVC08D
SN74ALVC08DG4
SN74ALVC08DG4
SN74ALVC08DGVR
SN74ALVC08DGVR
SN74ALVC08DR
SN74ALVC08DR
SN74ALVC08DRE4
SN74ALVC08DRE4
SN74ALVC08DRG4
SN74ALVC08DRG4
SN74ALVC08NSR
SN74ALVC08NSR
SN74ALVC08PWR
SN74ALVC08PWR
SN74ALVC08PWRE4
SN74ALVC08PWRE4
SN74ALVC08PWRG4
SN74ALVC08PWRG4
SN74ALVC08RGYR
SN74ALVC08RGYR
SN74ALVC08RGYRG4
SN74ALVC08RGYRG4
Bits444444444444
ICC @ Nom Voltage(Max), mA0.010.010.010.010.010.010.010.010.010.010.010.01
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA-24/24-24/24-24/24-24/24-24/24-24/24-24/24-24/24-24/24-24/24-24/24-24/24
Package GroupSOICSOICTVSOPSOICSOICSOICSOTSSOPTSSOPTSSOPVQFNVQFN
Package Size: mm2:W x L, PKG14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14TVSOP: 23 mm2: 6.4 x 3.6(TVSOP)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SO: 80 mm2: 7.8 x 10.2(SO)14TSSOP: 32 mm2: 6.4 x 5(TSSOP)14TSSOP: 32 mm2: 6.4 x 5(TSSOP)14TSSOP: 32 mm2: 6.4 x 5(TSSOP)14VQFN: 12 mm2: 3.5 x 3.5(VQFN)14VQFN: 12 mm2: 3.5 x 3.5(VQFN)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNoNoNoNoNoNoNo
Technology FamilyALVCALVCALVCALVCALVCALVCALVCALVCALVCALVCALVCALVC
VCC(Max), V3.63.63.63.63.63.63.63.63.63.63.63.6
VCC(Min), V1.651.651.651.651.651.651.651.651.651.651.651.65
Voltage(Nom), V1.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.31.8,2.5,2.7,3.3
tpd @ Nom Voltage(Max), ns5.3,3.3,3,2.95.3,3.3,3,2.95.3,3.3,3,2.95.3,3.3,3,2.95.3,3.3,3,2.95.3,3.3,3,2.95.3,3.3,3,2.95.3,3.3,3,2.95.3,3.3,3,2.95.3,3.3,3,2.95.3,3.3,3,2.95.3,3.3,3,2.9

生态计划

SN74ALVC08DSN74ALVC08DG4SN74ALVC08DGVRSN74ALVC08DRSN74ALVC08DRE4SN74ALVC08DRG4SN74ALVC08NSRSN74ALVC08PWRSN74ALVC08PWRE4SN74ALVC08PWRG4SN74ALVC08RGYRSN74ALVC08RGYRG4
RoHSCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliant

应用须知

  • TI SN74ALVC16835 Component Specification Analysis for PC100
    PDF, 43 Kb, 档案已发布: Aug 3, 1998
    The PC100 standard establishes design parameters for the PC SDRAM DIMM that is designed to operate at 100 MHz. The 168-pin, 8-byte, registered SDRAM DIMM is a JEDEC-defined device (JC-42.5-96-146A). Some of the defined signal paths include data signals, address signals, and control signals. This application report discusses the SN74ALVC16835 18-bit universal bus driver that is available from T
  • Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)
    PDF, 96 Kb, 修订版: A, 档案已发布: May 13, 1998
    Design of high-performance personal computer (PC) systems that are capable of meeting the needs imposed by modern operating systems and software includes the use of large banks of SDRAMs on DIMMs (see Figure 1).To meet the demands of stable functionality over the broad spectrum of operating environments, meet system timing needs, and to support data integrity, the loads presented by the large
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, 修订版: B, 档案已发布: May 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Understanding Advanced Bus-Interface Products Design Guide
    PDF, 253 Kb, 档案已发布: May 1, 1996
  • Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)
    PDF, 154 Kb, 修订版: A, 档案已发布: Sep 8, 1999
    In the last few years the trend toward reducing supply voltage (VCC) has continued as reflected in an additional specification of 2.5-V VCC for the AVC ALVT ALVC LVC LV and the CBTLV families.In this application report the different logic levels at VCC of 5 V 3.3 V 2.5 V and 1.8 V are compared. Within the report the possibilities for migration from 5-V logic and 3.3-V logic families

模型线

制造商分类

  • Semiconductors> Logic> Gate> AND Gate