Datasheet Texas Instruments SN65LVDS96DGG — 数据表
| 制造商 | Texas Instruments |
| 系列 | SN65LVDS96 |
| 零件号 | SN65LVDS96DGG |
Serdes（串行器/解串器）接收器48-TSSOP
数据表
价格
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
打包
| Pin | 48 |
| Package Type | DGG |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 40 |
| Carrier | TUBE |
| Device Marking | SN65LVDS96 |
| Width (mm) | 6.1 |
| Length (mm) | 12.5 |
| Thickness (mm) | 1.15 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1.2 |
| Mechanical Data | 下载 |
参数化
| Operating Temperature Range | -40 to 85 C |
| Output Compatibility | LVTTL |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 48TSSOP: 101 mm2: 8.1 x 12.5(TSSOP) PKG |
| Protocols | Channel-Link I |
| Rating | Catalog |
| Supply Voltage(s) | 3.3 V |
生态计划
| RoHS | Compliant |
应用须知
- LVDS Serdes 48 EVM Kit Setup And UsagePDF, 735 Kb, 档案已发布: Dec 17, 1998
This document describes the Texas Instruments (TI)(tm) LVDS Serdes 48 evaluation module (EVM) kit. The LVDS Serdes 48 EVM kit is used to evaluate and design high data throughput prototypes using the TI LVDS95 transmitter and LVDS96 receiver boards. The boards allow the designer to connect 21 bits of data and clock to the transmitter board where LVDS technology is available to serialize and transm
模型线
系列: SN65LVDS96 (4)
- SN65LVDS96DGG SN65LVDS96DGGG4 SN65LVDS96DGGR SN65LVDS96DGGRG4
制造商分类
- Semiconductors > Interface > LVDS/M-LVDS/PECL > SerDes/Channel-Link