Datasheet Texas Instruments SN65LVDS314RSKR — 数据表

SN65LVDS314
www.ti.com SLLSE98A – AUGUST 2012 – REVISED SEPTEMBER 2012 PROGRAMMABLE 27-BIT SERIAL-TO-PARALLEL RECEIVER
Check for Samples: SN65LVDS314 FEATURES 1 2 Serial Interface Technology
Compatible with FlatLinkв„ў3G such as
SN65LVDS301 and SN65LVDS311
Supports Video Interfaces up to 24-bit RGB
Data and 3 Control Bits Received over 1, 2 or 3
SubLVDS Differential Lines
SubLVDS Differential Voltage Levels
Flexible RGB Signaling Level of 1.8 V to 3.3 V
Up to 1.755 Gbps Data Throughput
Three Operating Modes to Conserve Power
– Active mode QVGA -17 mW
– Typical Shutdown -0.6 μW
– Typical Standby Mode -54 μW Typical
Bus-Swap Function for PCB-Layout Flexibility
ESD Rating > 4 kV (HBM)
Pixel Clock Range of 4 MHz–65 MHz
Failsafe on all CMOS Inputs
Packaged in 8 mm x 8 mm QFN with 0.4 mm
pin pitch
Very low EMI meets SAE J1752/3 'Kh'-spec APPLICATIONS The serial data and clock are received via Sub LowVoltage Differential Signalling (SubLVDS) lines. The
SN65LVDS314 supports three operating power …